Circuit substrate and method for manufacturing the same
AssigneeKYOCERA Corporation
InventorsMotohiro Umehara, Yoshinori Kubo
Life of this patent
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Abstract
A method for manufacturing a circuit substrate including an insulation substrate formed with a plurality of via holes passing through a first main surface and a second main surface and a metal with which the via holes are filled, the first and second main surfaces being opposing main surfaces, comprising forming, in the insulation substrate, the via hole or a non-through hole opening only on the second main surface; filling the via hole or the non-through hole with the metal; polishing the metal of at least one of the main surfaces to form a step between the metal and the insulation substrate; coating a polished surface of the metal by plating; and polishing the metal on the first main surface and the second main surface.
Claims15
A circuit substrate comprising:
- an insulation substrate formed with a plurality of via holes passing through a first main surface and a second main surface, the first main surface and the second main surface being opposing main surfaces;
- a second metal layer with which the plurality of via holes are filled;
- and
- a third metal layer coating an entire surface of the second metal layer,
- wherein the second metal layer is a plated metal, and the third metal layer is a plated metal,
- wherein the third metal layer is denser and harder than the second metal layer, and
- wherein an interface between the second metal layer and the third metal layer is located between the first main surface and the second main surface in the via hole, and the interface between the second metal layer and the third metal layer is a polished surface.
A circuit substrate comprising:
- an insulation substrate formed with a plurality of via holes passing through a first main surface and a second main surface, the first main surface and the second main surface being opposing main surfaces;
- a second metal layer with which the plurality of via holes are filled;
- and
- a third metal layer coating an entire surface of the second metal layer,
- wherein the second metal layer is a plated metal, and the third metal layer is a plated metal,
- wherein a first arithmetic average roughness Ra of at least one of the opposing main surfaces and a second arithmetic average roughness Ra of a surface of the third metal layer are equal to or less than 0.3 μm, and a difference between the first arithmetic average roughness Ra and the second arithmetic average roughness Ra is equal to or less than 0.2 μm, and
- wherein an interface between the second metal layer and the third metal layer is located between the first main surface and the second main surface in the via hole, and the interface between the second metal layer and the third metal layer is a polished surface.
Dependencies are inferred from the claim text.