High-speed signaling systems with adaptable pre-emphasis and equalization

A first integrated circuit (IC), comprising:

• transmit circuitry to transmit, from the first IC to a second IC that is separate from the first IC, a digital bit stream;
• receiver circuitry disposed on the first IC to receive a setting from the second IC based on an updated setting of a decision feedback equalizer (DFE) of the second IC, the setting generated by a control circuit on the second IC;
• and
• wherein the updated setting is based on a measure of quality of the digital bit stream as received by the second IC.

A first integrated circuit (IC) chip, comprising:

• a transmitter to transmit, from the first IC chip to a second IC chip that is separate from the first IC chip, a digital bit stream;
• a receiver disposed on the first IC chip to receive a setting from the second IC chip based on an updated setting of an equalizer of the second IC chip, the updated setting generated by a control circuit on the second IC chip;
• and
• wherein the updated setting is based on a measure of quality of the digital bit stream as received by the second IC chip.