Error correcting code encoding circuit and semiconductor device including the same

A semiconductor device comprising:

• an error correcting code (ECC) encoder configured to encode a codeword based on a parity check matrix and to generate an encoded codeword (ECW) including an information bit and a parity bit,
• wherein the ECC encoder includes:
• a parity check matrix (PCM) generator configured to generate the parity check matrix;
• and
• an encoding unit coupled to the PCM generator and configured to generate the encoded codeword based on the codeword and the parity check matrix;
• wherein the parity check matrix is divided into an information part corresponding to the information bit and a parity part corresponding to the parity bit, and
• wherein the parity part includes:
• a plurality of sub-rows and a plurality of sub-columns;
• a block matrix T including a plurality of first sub-matrices arranged in a dual diagonal structure;
• a block matrix B including:
• a first column vector positioned in a first sub-column of the plurality of sub-columns and including a (1−a1)-th sub-matrix, a1 being an integer greater than or equal to 0, and
• a second column vector positioned in a second sub-column of the plurality of sub-columns and including a (1−a2)-th sub-matrix, a2 being an integer greater than or equal to 0;
• a block matrix E including:
• a first row vector positioned in a first sub-row of the plurality of sub-rows and including a first sub-matrix, and
• a second row vector positioned in a second sub-row of the plurality of sub-rows and including the first sub-matrix;
• and
• a block matrix D including:
• a masked (1−(a1+1))-th sub-matrix positioned in the first sub-column and the first sub-row,
• a (1−(a1−2))-th sub-matrix positioned in the first sub-column and the second sub-row, and
• a masked (1−(a2+1))-th sub-matrix positioned in the second sub-column and the second sub-row,
• wherein a location where the (1−a1)-th sub-matrix of the block matrix B is placed in the first column vector precedes a location where the first sub-matrix of the block matrix E is placed in the first row vector,
• wherein a location where the (1−a2)-th sub-matrix of the block matrix B is placed in the second column vector precedes a location where the first sub-matrix of the block matrix E is placed in the second row vector,
• wherein the first sub-matrix is defined as a unit matrix having a size of Z×Z, Z being a natural number,
• wherein the (1−aj)-th sub-matrix is defined as a matrix obtained by performing a left-cyclic shift ‘aj’ times on the first sub-matrix, j being 1 or 2,
• wherein the masked (1−(aj+1))-th sub-matrix is defined as a matrix in which a first row is masked in a matrix obtained by performing a left-cyclic shift “aj+1” times on the first sub-matrix, and
• wherein the (1−(aj−2))-th sub-matrix is defined as a matrix obtained by performing a left-cyclic shift “aj−2” times on the first sub-matrix.