Voltage regulator for switch control

An integrated circuit (IC) comprising:

• a first resistor having a first terminal, a second terminal, and resistance R1;
• N p-channel field-effect transistors (ladder PFETS), each ladder PFET having a source, a drain, and a gate, in which N is greater than or equal to one, wherein if N is greater than one the ladder PFETS are coupled together as a p-ladder, so that the gates of the ladder PFETS are coupled together, the drains and sources of the ladder PFETS are cascade-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor;
• a differential amplifier including a first input, a second input, and an output;
• a second resistor having a first terminal, a second terminal, and resistance y×R1, in which y is an integer greater than or equal to one so that y×N is greater than one, and a first terminal of the second resistor is coupled to the second terminal of the first resistor and the first input of the differential amplifier;
• y×N−1 third resistors, each of the third resistors having a resistance R2;
• and
• y×N n-channel field-effect transistors (ladder NFETS) coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the drains and sources of the ladder NFETS cascade-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier;
• wherein different pairs of the ladder NFETS that are adjacently coupled drain-to-source within the n-ladder have respective gates coupled together via different ones of the third resistors.

A digital-to-analog converter system comprising:

• a gate driver including a first input, a second input, and multiple outputs;
• a control circuit including a input and an output, the output of the control circuit coupled to the first input of the gate driver;
• an R2R resistor ladder including multiple arms coupled together, at least some of the arms respectively including a p-channel field-effect transistor (PFET) switch and an n-channel field-effect transistor (NFET) switch, in which a source of the NFET switch is coupled to a source of the PFET switch and a gate of the NFET switch is coupled to a different one of the outputs of the gate driver than the gates of the NFET switches of the other arms;
• and
• a voltage regulator including:
• a first resistor having a first terminal, a second terminal, and resistance R1;
• N ladder PFETS, each ladder PFET having a source, a drain, and a gate, in which N is an integer greater than or equal to one, wherein if N is greater than one the ladder PFETS are coupled together as a p-ladder, so that the gates of the ladder PFETS are coupled together, the drains and sources of the ladder PFETS are cascade-coupled between a first end and a second end of the p-ladder, and the second end of the p-ladder is coupled to the first terminal of the first resistor;
• a differential amplifier including a first input, a second input, and an output, the output of the differential amplifier coupled to the second input of the gate driver;
• a second resistor having a first terminal, a second terminal, and resistance y×R1, in which y is an integer greater than one, and a first terminal of the second resistor is coupled to the second terminal of the first resistor and the first input of the differential amplifier;
• and
• y×N ladder NFETS coupled together as an n-ladder, each ladder NFET having a source, a drain, and a gate, the gates of the ladder NFETS coupled together, the drains and sources of the ladder NFETS cascade-coupled between a first end and a second end of the n-ladder, the first end of the n-ladder coupled to the second terminal of the second resistor, and the second end of the n-ladder coupled to the output of the differential amplifier.