Continuous-time ADC calibration techniques
AssigneeAnalog Devices International Unlimited Company
InventorsAsha Ganesan, Donald W. Paterson, Sharvil Pradeep Patil, Nevena Rakuljic
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Abstract
CT ADCs based on continuous-time residue generation systems require accurate estimation of analog transfer functions. This is done by using a pseudo random bit sequence, injected using a DAC, that traverses the transfer function to be measured. Mismatch in the injection DAC introduces errors in the transfer function estimation and results in poor NSD at the ADC output. Techniques are described to improve the accuracy of the transfer function estimate despite DAC mismatch and despite the presence of an input signal.
Claims20
A continuous-time (CT) analog-to-digital converter (ADC), comprising:
- a delay circuit configured to generate a delay circuit output signal by applying a delay to an analog input signal;
- a sub-ADC circuit configured to generate a sub-ADC circuit output signal based on the analog input signal;
- a first sub-DAC circuit coupled to receive the sub-ADC circuit output signal and generate an analog representation of the sub-ADC circuit output signal, wherein the analog representation of the sub-ADC circuit output signal is combined with the delay circuit output signal to generate a residue signal;
- an error estimation circuit configured to receive an ADC output signal and generate an error estimation circuit signal;
- an error correction circuit configured to receive the error estimation circuit signal and generate a digital error-correction signal;
- and
- an output node coupled to an input of the error estimation circuit and configured to generate the ADC output signal using:
- 1) the residue signal, 2) the sub-ADC circuit output signal, and 3) the digital error-correction signal.
A method of operating a continuous-time (CT) analog-to-digital converter (ADC), the method comprising:
- applying a delay to an analog input signal to generate a delay circuit output signal;
- generating a sub-ADC circuit output signal based on the analog input signal;
- receiving, via a first sub-DAC circuit, the sub-ADC circuit output signal and generating an analog representation of the sub-ADC circuit output signal;
- generating a residue signal by combining an analog representation of the sub-ADC circuit output signal with the delay circuit output signal;
- receiving an ADC output signal and generating an error estimation circuit signal;
- receiving the error estimation circuit signal and generating a digital error-correction signal;
- and
- generating the ADC output signal at an output node using:
- 1) the residue signal, 2) the sub-ADC circuit output signal, and 3) the digital error-correction signal.
A continuous-time (CT) analog-to-digital converter (ADC), comprising:
- a delay circuit configured to generate a delay circuit output signal by applying a delay to an analog input signal;
- a sub-ADC circuit configured to generate a sub-ADC circuit output signal based on the analog input signal;
- a first sub-DAC circuit coupled to receive the sub-ADC circuit output signal and generate an analog representation of the sub-ADC circuit output signal, wherein the analog representation of the sub-ADC circuit output signal is combined with the delay circuit output signal to generate a residue signal;
- means for receiving an ADC output signal and generating an error estimation circuit signal;
- means for receiving the error estimation circuit signal and generating a digital error-correction signal;
- and
- an output node coupled to an input of the means for receiving the ADC output signal and generating the error estimation circuit signal and configured to generate the ADC output signal using:
- 1) the residue signal, 2) the sub-ADC circuit output signal, and 3) the digital error-correction signal.
Dependencies are inferred from the claim text.