Voltage-to-delay converter

A method, comprising:

• charging a first plate of each of first and second integrating capacitors to a first voltage;
• applying a differential voltage across first and second inputs, the first input coupled to a gate terminal of a first transistor coupled between the first plate of the first integrating capacitor and a reference potential, and the second input coupled to a gate terminal of a second transistor coupled between the first plate of the second integrating capacitor and the reference potential;
• discharging a second plate of each of the first and second integrating capacitors toward the reference potential;
• and
• then generating first and second pulses having a relative delay corresponding to voltages at the first plates of the first and second integrating capacitors;
• and
• generating a digital output word corresponding to the relative delay of the first and second pulses.

An analog-to-digital converter, comprising:

• a voltage-to-delay converter, comprising:
• a first reset transistor having a first terminal coupled to a power supply terminal, and having a gate terminal coupled to receive a reset signal;
• a first integrating capacitor having a first terminal coupled to a second terminal of the first reset transistor and having a second terminal;
• a second reset transistor having a first terminal coupled to the power supply terminal, and having a gate terminal coupled to receive the reset signal;
• a second integrating capacitor having a first terminal coupled to a second terminal of the second reset transistor and having a second terminal;
• a first current source having a first terminal coupled to a common potential;
• a first input transistor having a first terminal coupled to a second terminal of the first current source, a second terminal coupled to the first terminal of the first integrating capacitor, and a gate terminal coupled to receive a first input voltage;
• a second input transistor having a first terminal coupled to the second terminal of the first current source, a second terminal coupled to the first terminal of the second integrating capacitor, and a gate terminal coupled to receive a second input voltage;
• a discharge current source having a first terminal coupled to a second terminal of each of the first and second integrating capacitors, and a second terminal coupled to the common potential;
• and
• a pulse generator having a first input coupled to the first terminal of the first integrating capacitor, a second input coupled to the first terminal of the second integrating capacitor, and first and second outputs;
• and
• a delay-to-digital converter, having first and second inputs coupled to the first and second outputs of the pulse generator, respectively, and having a digital output, the delay to digital converter configured to generate a digital output word corresponding to a relative delay between pulses at the first and second outputs of the pulse generator.