Electrostatic discharge (ESD) protection circuit and method of operating the same
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsTao Yi Hung, Ming-Fang Lai, Li-Wei Chu, Wun-Jie Lin, Jam-Wem Lee
Life of this patent
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Abstract
A clamp circuit includes an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node. The clamp circuit further includes a first transistor of a first type. The first transistor has a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node. The clamp circuit further includes a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node.
Claims20
A clamp circuit comprising:
- an electrostatic discharge (ESD) detection circuit coupled between a first node and a second node;
- a first transistor of a first type, the first transistor comprising a first well, a first gate coupled to at least the ESD detection circuit by a third node, a first drain coupled to the first node and a first source coupled to the second node, at least the first transistor is in a semiconductor wafer, the semiconductor wafer including a front-side and a back-side opposite from the front-side, the first transistor being in the front-side of the semiconductor wafer;
- a charging circuit coupled between the second node and the third node, and configured to charge the third node during an ESD event at the second node;
- and
- a first conductive structure on the back-side of the semiconductor wafer, the first conductive structure being coupled to the second node, extending completely through the back-side of the semiconductor wafer, extending into the first well and is directly coupled to the first source of the first transistor.
An electrostatic discharge (ESD) protection circuit, comprising:
- a first diode coupled between a first node and an input output (IO) pad;
- a second diode coupled between the IO pad and a second node;
- an internal circuit coupled to the first diode, the second diode and the IO pad;
- and
- a clamp circuit between the first node and the second node, the clamp circuit comprising:
- an ESD detection circuit coupled between the first node and the second node;
- a discharging circuit coupled between the first node and the second node, and coupled to the ESD detection circuit by a third node, wherein the discharging circuit comprises:
- a first transistor of a first type, the first transistor comprising a first well and a first source in the first well, at least the first transistor is in a semiconductor wafer, the semiconductor wafer including a front-side and a back-side opposite from the front-side, the first transistor being in the front-side of the semiconductor wafer;
- a charging circuit coupled between the second node and the third node, and
- configured to charge the third node during an ESD event at the second node;
- and
- a first conductive structure on the back-side of the semiconductor wafer, the first conductive structure being coupled to the second node, extending into the first well, being directly coupled to the first source of the first transistor and extending completely through the back-side of the semiconductor wafer.
A method of operating an electrostatic discharge (ESD) circuit, the method comprising:
- receiving a first ESD voltage on a first node, the first ESD voltage being greater than a reference supply voltage of a reference voltage supply, the first ESD voltage corresponding to a first ESD event;
- detecting, by a charging circuit, the first ESD event at the first node thereby causing the charging circuit to turn on and charge a gate of a first transistor of a discharging circuit, the discharging circuit being coupled between the first node and a second node, and the charging circuit being coupled between at least the first node and a third node, at least the first transistor is in a semiconductor wafer, the semiconductor wafer including a front-side and a back-side opposite from the front-side, the first transistor being in the front-side of the semiconductor wafer, the second node being coupled to a first conductive structure on the back-side of the semiconductor wafer, the first conductive structure extends completely through the back-side of the semiconductor wafer, extends into a first source of the first transistor and is directly coupled to the first source of the first transistor;
- and
- discharging a first ESD current of the first ESD event in a first ESD direction from the first node to the second node by a channel of the first transistor.
Dependencies are inferred from the claim text.