Devices with reduced capacitances

A device structure, comprising:

• a via structure disposed in a first dielectric layer;
• an etch stop layer (ESL) over the first dielectric layer;
• a second dielectric layer over the ESL;
• a first metal feature and a second metal feature disposed in the ESL and the second dielectric layer, the first metal feature being disposed over the via structure and the second metal feature being disposed over the first dielectric layer;
• a first diffusion barrier layer extending continuously between the first metal feature and the second dielectric layer, between the first metal feature and the ESL, and between the first metal feature and the via structure;
• a second diffusion barrier layer extending continuously between the second metal feature and the second dielectric layer, between the second metal feature and the ESL, and between the second metal feature and the first dielectric layer;
• a first protecting layer disposed between the first diffusion barrier layer and the second dielectric layer;
• a second protecting layer disposed between the second diffusion barrier layer and the second dielectric layer;
• and
• an air gap disposed in the second dielectric layer between the first protecting layer and the second protecting layer,
• wherein the second dielectric layer comprises a low-k dielectric material,
• wherein top surfaces of the first metal feature, the second metal feature, the first diffusion barrier layer, the second diffusion barrier layer, the first protecting layer, the second protecting layer, and the second dielectric layer are coplanar.

A device, comprising:

• a first conductive feature embedded within a first dielectric layer and electrically connected to a source/drain feature on a semiconductor substrate, top surfaces of the first conductive feature and the first dielectric layer being coplanar;
• an etch stop layer over the top surface of the first dielectric layer;
• a second dielectric layer over the etch stop layer;
• a second conductive feature disposed over and electrically coupled to the first conductive feature, the second conductive feature being disposed in the etch stop layer and the second dielectric layer;
• a third conductive feature on the first dielectric layer and disposed in the etch stop layer and the second dielectric layer;
• an air gap between the second conductive feature and the third conductive feature and embedded within the second dielectric layer;
• a first metal capping layer over the second conductive feature;
• a second metal capping layer over the third conductive feature;
• and
• a first barrier layer extending continuously from along a first sidewall of the second conductive feature, to along a bottom surface of the second conductive feature, and to along a second sidewall of the second conductive feature,
• wherein the first barrier layer interfaces a top surface of the first conductive feature.