# US 12,444,444 B2 · Multi-write read-only memory array > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,444,444 B2 - Document ID: US12444444B2 - Status: Granted - Kind: B2 - Application number: 18/529,115 - Filed: 2023-12-05 - Published: 2025-04-03 - Granted: 2025-10-14 - Earliest claimed: 2023-10-03 - Assignees: Yield Microelectronics Corp. - Applicants: Yield Microelectronics Corp. - Inventors: Yu-Ting Huang; Chi-Pei Wu - Web page: https://patentgrep.com/patent/US12444444B2 ## CPC - G11C 5/063: {Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay} - G11C 5/025: {Geometric lay-out considerations of storage- and peripheral-blocks in a semiconductor storage device (geometrical lay-out of the components in integrated circuits, geometrical lay-out of the components in integrated circuits H10D89/10)} - G11C 7/18: Bit line organisation; Bit line lay-out - G11C 16/10: Programming or data input circuits - G11C 16/14: Circuits for erasing electrically, e.g. erase voltage switching circuits - G11C 16/0416: {comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM} - G11C 17/16: using electrically-fusible links - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A multi-write read-only memory array includes word common-source lines, bit lines, and sub-memory arrays. The word common-source lines include a first word common-source line and a second word common-source line. The bit lines include a first bit line and a second bit line. Each sub-memory array includes a first memory cell coupled to the first word common-source line and the first bit line, a second memory cell coupled to the first word common-source line and the second bit line, a third memory cell coupled to the second word common-source line and the second bit line, and a fourth memory cell coupled to the second word common-source line and the first bit line. ## Claims ### Claim 1 A multi-write read-only memory array comprising: a plurality of word common-source lines, arranged in parallel, comprising a first word common-source line and a second word common-source line; a plurality of bit lines arranged in parallel, wherein the plurality of bit lines perpendicular to the plurality of word common-source lines comprise a first bit line and a second bit line; and a plurality of sub-memory arrays each coupled to two of the plurality of word common-source lines and two of the plurality of bit lines, wherein each of the plurality of sub-memory arrays comprises: a first memory cell coupled to the first word common-source line and the first bit line; a second memory cell coupled to the first word common-source line and the second bit line; a third memory cell coupled to the second word common-source line and the second bit line; and a fourth memory cell coupled to the second word common-source line and the first bit line. ### Claim 2 (depends on 1) The multi-write read-only memory array according to claim 1, wherein the first memory cell and the second memory cell are symmetric about the first word common-source line, the third memory cell and the fourth memory cell are symmetric about the second word common-source line, and the second memory cell and the third memory cell are located between the first memory cell and the fourth memory cell. ### Claim 3 (depends on 2) The multi-write read-only memory array according to claim 2, wherein the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell are formed in a semiconductor region having a first conductivity type, and the first memory cell, the second memory cell, the third memory cell, and the fourth memory cell commonly comprise: a first gate dielectric block, a second gate dielectric block, a third gate dielectric block, and a fourth gate dielectric block respectively formed on the semiconductor region; a first conductive gate, a second conductive gate, a third conductive gate, and a fourth conductive gate respectively formed on the first gate dielectric block, the second gate dielectric block, the third gate dielectric block, and the fourth gate dielectric block; a first heavily-doped area and a second heavily-doped area formed in the semiconductor region, respectively formed on two opposite side of the semiconductor region, which is directly arranged under the first conductive gate, and respectively coupled to the first bit line and the first word common-source line, wherein the first heavily-doped area and the second heavily-doped area have a second conductivity type opposite to the first conductivity type; a third heavily-doped area formed in the semiconductor region, the second heavily-doped area and the third heavily-doped area are respectively formed on two opposite side of the semiconductor region, which is directly arranged under the second conductive gate, the third heavily-doped area is coupled to the second bit line, and the third heavily-doped area has the second conductivity type; a fourth heavily-doped area formed in the semiconductor region, the third heavily-doped area and the fourth heavily-doped area are respectively formed on two opposite side of the semiconductor region, which is directly arranged under the third conductive gate, the fourth heavily-doped area is coupled to the second word common-source line, and the fourth heavily-doped area has the second conductivity type; and a fifth heavily-doped area formed in the semiconductor region, the fourth heavily-doped area and the fifth heavily-doped area are respectively formed on two opposite side of the semiconductor region, which is directly arranged under the fourth conductive gate, the fifth heavily-doped area is coupled to the first bit line, and the fifth heavily-doped area has the second conductivity type. ### Claim 4 (depends on 3) The multi-write read-only memory array according to claim 3, wherein the first conductivity type is a P type and the second conductivity type is an N type. ### Claim 5 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is selected to perform a programming activity, the semiconductor region is coupled to a grounding voltage, the first bit line is coupled to a middle voltage or the grounding voltage, and the first word common-source line is coupled to the middle voltage or a high voltage, wherein the high voltage is greater than the middle voltage and the middle voltage is greater than the grounding voltage. ### Claim 6 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is not selected to perform a programming activity, the semiconductor region is coupled to a grounding voltage, the first bit line is electrically floating or coupled to a low voltage, and the first word common-source line is coupled to the grounding voltage, wherein the low voltage is greater than the grounding voltage. ### Claim 7 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is selected to perform an erasing activity, the semiconductor region is coupled to a grounding voltage, the first bit line is coupled to a high voltage, and the first word common-source line is coupled to the grounding voltage, wherein the high voltage is greater than the grounding voltage. ### Claim 8 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is not selected to perform an erasing activity, the semiconductor region is coupled to a grounding voltage, the first bit line is electrically floating, and the first word common-source line is coupled to a low voltage or a middle voltage, wherein the middle voltage is greater than the low voltage and the low voltage greater than the grounding voltage. ### Claim 9 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is selected to perform a reading activity, the semiconductor region and the first bit line are coupled to a grounding voltage and the first word common-source line is coupled to a low voltage, wherein the low voltage is greater than the grounding voltage. ### Claim 10 (depends on 4) The multi-write read-only memory array according to claim 4, wherein when the first memory cell is not selected to perform a reading activity, the semiconductor region, the first bit line, and the first word common-source line are coupled to a grounding voltage. ### Claim 11 (depends on 3) The multi-write read-only memory array according to claim 3, wherein the first conductivity type is an N type and the second conductivity type is a P type. ### Claim 12 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is selected to perform a programming activity, the semiconductor region is coupled to a high voltage, the first bit line is coupled to a middle voltage or the high voltage, and the first word common-source line is coupled to the middle voltage or a grounding voltage, wherein the high voltage is greater than the middle voltage and the middle voltage is greater than the grounding voltage. ### Claim 13 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is not selected to perform a programming activity, the semiconductor region is coupled to a high voltage, the first bit line is electrically floating or coupled to a middle voltage, and the first word common-source line is coupled to the high voltage, wherein the high voltage is greater than the middle voltage. ### Claim 14 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is selected to perform an erasing activity, the semiconductor region is coupled to a high voltage, the first bit line is coupled to a grounding voltage, and the first word common-source line is coupled to the high voltage, wherein the high voltage is greater than the grounding voltage. ### Claim 15 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is not selected to perform an erasing activity, the semiconductor region is coupled to a high voltage, the first bit line is electrically floating, and the first word common-source line is coupled to a middle voltage, wherein the high voltage is greater than the middle voltage. ### Claim 16 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is selected to perform a reading activity, the semiconductor region and the first bit line are coupled to a middle voltage and the first word common-source line is coupled to a low voltage, wherein the middle voltage is greater than the low voltage. ### Claim 17 (depends on 11) The multi-write read-only memory array according to claim 11, wherein when the first memory cell is not selected to perform a reading activity, the semiconductor region, the first bit line, and the first word common-source line are coupled to a middle voltage, wherein the middle voltage is greater than the grounding voltage. ### Claim 18 (depends on 3) The multi-write read-only memory array according to claim 3, wherein the semiconductor region is a semiconductor substrate or an epitaxial layer formed on a semiconductor substrate.