Display data bus power reduction via data bus gating
AssigneeApple Inc.
InventorYoung Don Bae
Life of this patent
Estimating the term…
Abstract
In electronic displays, sending image data across a pixel data bus to the source latches consumes energy, particularly as the number of columns of pixels of the electronic display increases. To reduce the amount of energy consumed by the pixel data bus, slices of the pixel data bus may be gated to correspond to which source latches are being loaded. For instance, a first set of source latches corresponding to a first slice of the pixel data bus may be loaded with data while downstream slices of the pixel data bus may be gated to save energy. To reduce the peak energy consumed by the pixel data bus, the pixel data bus may be divided into two parts that are loaded from opposite sides. Thus, the total number of gated slices may remain stable throughout the loading process.
Claims20
An electronic display, comprising:
- a plurality of pixels in a pixel array;
- a timing controller configured to receive image data;
- and
- a data bus comprising:
- a first slice that is initially gated;
- a second slice that is initially gated;
- and
- control circuitry configured to ungate the first slice to enable the first slice to receive the image data from the timing controller, and ungate the second slice after ungating the first slice to enable the second slice to receive the image data passed from the first slice.
A data bus, comprising:
- a first portion comprising a first slice and a second slice, the first portion configured to receive first image data from a timing controller in a first direction;
- and
- first control circuitry coupled to the first slice and the second slice, the first control circuitry configured to ungate the first slice and the second slice sequentially as the first image data is directly transferred from the first slice to the second slice.
An electronic display, comprising:
- a plurality of pixels in a pixel array;
- and
- a data bus comprising:
- a first portion comprising a first slice and a second slice configured to load image data by directly transferring the image data from the first slice to the second slice in a first direction;
- and
- a second portion comprising a third slice and a fourth slice configured to load the image data by directly transferring the image data from third slice to the fourth slice in a second direction, the second direction different than the first direction.
A data bus, comprising:
- a first portion comprising a first slice and a second slice, the first portion configured to receive first image data in a first direction;
- and
- first control circuitry coupled to the first slice and the second slice, the first control circuitry configured to ungate the first slice to enable the first image data to be transferred to the first slice, and ungate the second slice sequentially to the first slice to enable the first image data to be directly transferred from the first slice to the second slice.
Dependencies are inferred from the claim text.