Neural network accelerator in DIMM form factor
AssigneeGoogle Inc.
InventorsDoe Hyun Yoon, Lifeng Nai, Peter Ma
Life of this patent
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Abstract
The technology relates to a neural network dual in-line memory module (NN-DIMM), a microelectronic system comprising a CPU and a plurality of the NN-DIMMs, and a method of transferring information between the CPU and the plurality of the NN-DIMMS. The NN-DIMM may include a module card having a plurality of parallel edge contacts adjacent to an edge of a slot connector thereof and configured to have the same command and signal interface as a standard dual in-line memory module (DIMM). The NN-DIMM may also include a deep neural network (DNN) accelerator affixed to the module card, and a bridge configured to transfer information between the DNN accelerator and the plurality of parallel edge contacts via a DIMM external interface.
Claims20
A neural network dual in-line memory module (NN-DIMM), comprising:
- a module card having a plurality of parallel edge contacts adjacent an edge of a slot connector thereof and configured to have the same command and signal interface as a standard dual in-line memory module (DIMM);
- a deep neural network (DNN) accelerator affixed to the module card;
- and
- a bridge configured to transfer information between the DNN accelerator and the plurality of parallel edge contacts via a DIMM external interface, and
- wherein the bridge includes control registers and on-chip memory are accessible as a standard DRAM to a host CPU, wherein the bridge is configured to map the control registers and the on-chip memory to one row of a plurality of banks of the NN-DIMM, and wherein access of the control registers or the on-chip memory is limited to the one row of the plurality of banks.
A microelectronic system comprising a CPU affixed to a motherboard, the CPU having a plurality of memory channels each including a respective neural network dual in-line memory module (NN-DIMM) electronically connected with the CPU, each NN-DIMM comprising:
- a module card having a plurality of parallel edge contacts adjacent an edge of a slot connector thereof and configured to have the same command and signal interface as a standard dual in-line memory module (DIMM);
- a deep neural network (DNN) accelerator affixed to the module card;
- and
- a bridge configured to transfer information between the DNN accelerator and the plurality of parallel edge contacts via a DIMM external interface, and
- wherein the bridge includes control registers and on-chip memory are configured to be accessed as a standard DRAM to a host CPU, wherein the bridge is configured to map the control registers and the on-chip memory to one row of a plurality of banks of the NN-DIMM, and wherein the control registers or the on-chip memory access is limited to the one row in the plurality of banks.
A method of transferring information between a host system CPU and a plurality of neural network dual in-line memory modules (NN-DIMMs), the method comprising:
- electrically connecting each of the NN-DIMMs to the host system CPU, the CPU having a plurality of memory channels each including a respective one of the NN-DIMMs, each of the NN-DIMMs comprising a deep neural network (DNN) accelerator and a bridge configured to transfer the information between the DNN accelerator and the host system CPU via a DIMM external interface, wherein the bridge of each of the NN-DIMMs includes control registers and on-chip memory that are seen as a standard DRAM to the host system CPU and wherein the bridge is configured to map the control registers and the on-chip memory to one row of a plurality of memory banks of the NN-DIMM;
- accessing, by the control registers or the on-chip memory, only the one row in the plurality of banks;
- and
- transferring the information between the host system CPU and the plurality of NN-DIMMs.
Dependencies are inferred from the claim text.