System and method for user interactive pipelining of a computing application

A Buffer Pipelined Application computing System (BPAS), the BPAS comprising:

• at least one hardware processor;
• at least one physical memory;
• a first stage processor configured to execute, utilizing a first hardware processor among the at least one hardware processor, a first execution stage among a plurality of application execution stages of a pipelined application;
• a second stage processor configured to execute, utilizing a second hardware processor among the at least one hardware processor, a second execution stage among the plurality of application execution stages;
• an application execution program (AEP) configured to execute, utilizing a third processor among the at least one hardware processor, operations to manage execution of the pipelined application by the system;
• a Pipeline Programming Interface (PPI);
• and,
• a Buffer-Pipeline Manager (BPM), the BPM configured to:
• allocate, responsive to a first interface of the PPI, based on execution parameters associated with the system executing the pipelined application, a plurality of pipeline buffers, the plurality of pipeline buffers included in memories among the at least one physical memory;
• configure access to a first buffer, among the plurality of pipeline buffers, by the first stage processor, the first buffer included in a first region of a first physical memory, the first physical memory among the at least one physical memory of the BPAS, the first stage processor further configured to execute the first execution stage utilizing the first buffer;
• initiate, responsive to the configuring the access to the first buffer by the first stage processor, operations of the first stage processor utilizing the first buffer;
• determine a first buffer ready status associated with a processing operation of the first stage processor on data included in the first buffer, the first data ready status corresponding to second stage input data ready for processing by the second stage processor, the second stage input data comprising data output by an operation of the first stage processor, the second stage processor further configured to execute the second execution stage to process the second stage input data;
• transfer, in response to the first buffer ready status, the first buffer to the second stage processor for processing, by the second stage processor, the second stage input data;
• and,
• configure, responsive to the transferring the first buffer, access by the second stage processor to a second buffer among the plurality of pipeline buffers, the second buffer including the second stage input data, the second buffer included in a second region of a second physical memory, the second memory among the at least one physical memory of the BPAS.

A computer program product, the computer program product comprising a computer readable storage medium having program instructions embodied therewith, wherein the program instructions are executable by at least one processor to cause the at least one processor to:

• allocate, responsive to a first interface of a Pipeline Programming Interface (PPI) of a Buffer Pipelined Application computing System (BPAS), based on execution parameters associated with the BPAS executing a pipelined application, a plurality of pipeline buffers, the pipelined application comprising a plurality of application execution stages, the BPAS comprising a plurality of stage processors to execute corresponding execution stages among plurality of application execution stages, the plurality of pipeline buffers included in at least one physical memory of the BPAS;
• configure access to a first buffer, among the plurality of pipeline buffers, by a first stage processor among the plurality of stage processors, the first buffer included in a first region of a first physical memory, the first physical memory among the at least one physical memory of the BPAS, the first stage processor to execute a first execution stage, among the plurality of application execution stages of the pipelined application, utilizing the first buffer;
• initiate, responsive to the configuring the access to the first buffer by the first stage processor, operations of the first stage processor utilizing the first buffer;
• determine a first buffer ready status associated with a processing operation of the first stage processor on data included in the first buffer, the first data ready status corresponding to second stage input data ready for processing by a second stage processor, the second stage input data comprising data output by an operation of the first stage processor, the second stage processor to execute a second execution stage, among the plurality of application execution stages, to process the second stage input data;
• transfer, responsive to the first buffer ready status, the first buffer to the second stage processor for processing, by the second stage processor, the second stage input data;
• and,
• configure, responsive to the transferring the first buffer, access by the second stage processor to a second buffer among the plurality of pipeline buffers, the second buffer including the second stage input data, the second buffer included in a second region of a second physical memory, the second memory among the at least one physical memory of the BPAS.