Processing pipeline with zero loop overhead

A processing pipeline, comprising:

• a data interface;
• and
• a plurality of processors operably connected to one another and capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function, the plurality of processors including a producer processor and a consumer processor, the producer processor being capable of providing, via the data interface, data to the consumer processor that is downstream from the producer processor with respect to the processing pipeline,
• wherein the producer processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in a first memory,
• wherein the consumer processor receives the processed data block based upon the processed data block being stored in the first memory,
• wherein the consumer processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in a second memory,
• wherein the producer processor and the consumer processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function,
• wherein the processing pipeline is part of a vector processing pipeline architecture, and
• wherein the commonly-executed function is implemented to perform a calculation of filter coefficients.

A processing pipeline, comprising:

• an upstream processor associated with a first memory;
• and
• a downstream processor associated with a second memory, the upstream processor and the downstream processor each being operably connected to a data interface;
• wherein the upstream processor and the downstream processor are capable of processing data blocks in accordance with a plurality of data processing loop iterations associated with a commonly-executed function,
• wherein the upstream processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory,
• wherein the downstream processor receives the processed data block based upon the processing of the data block by the upstream processor being completed,
• wherein the downstream processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory,
• wherein the upstream processor and the downstream processor are each capable of processing the data block and the processed data block, respectively, as part of continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function,
• wherein the processing pipeline is part of a vector processing pipeline architecture, and
• wherein the commonly-executed function is implemented to perform a calculation of filter coefficients.

A system, comprising:

• a first data interface capable of receiving data blocks from a data source as part of a data stream;
• and
• a processing pipeline comprising:
• a second data interface;
• a first processor associated with a first memory;
• and
• a second processor associated with a second memory, the second processor being operably coupled to the first processor via the second data interface and being downstream from the first processor in the processing pipeline,
• wherein the first processor and the second processor are capable of processing data blocks received via the first data interface in accordance with a plurality of data processing loop iterations associated with a commonly-executed function,
• wherein the first processor is capable of processing a data block in accordance with a first one of the plurality of data processing loop iterations to provide a processed data block, and storing the processed data block in the first memory,
• wherein the second processor receives the processed data block based upon the processed data block being stored in the first memory,
• wherein the second processor is capable of processing the processed data block in accordance with a second one of the plurality of data processing loop iterations and storing a result of processing the processed data block in the second memory,
• wherein the first processor and the second processor are each capable of processing the data block and the processed data block, respectively, as part of a continuous execution of the first and the second ones of the plurality of data processing loop iterations associated with the commonly-executed function,
• wherein the processing pipeline is part of a vector processing pipeline architecture, and
• wherein the commonly-executed function is implemented to perform a calculation of filter coefficients.