Memory system and method
AssigneeSony Group Corporation
InventorsYuji Takahashi, Hirokazu Hanaki
Life of this patent
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Abstract
A memory system (100) includes a memory (2) including a plurality of pages (21) on each of which data can be arranged and a defragmenting device (4) that rearranges the data arranged on the plurality of pages (21). The memory (2) includes a plurality of tiles (22) each including one or more pages. Each of the plurality of tiles (22) is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different. The plurality of states include a low power consumption state different from a power-off state. The defragmenting device (4) rearranges the data such that the tile (22) in which high access frequency data are collected and the tile (22) in which low access frequency data are collected are present.
Claims18
A memory system comprising:
- a memory including a plurality of pages on each of which data can be arranged;
- a defragmenting device that rearranges the data arranged on the plurality of pages, wherein
- the memory includes a plurality of tiles each including one or more pages,
- each of the plurality of tiles is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different,
- the plurality of states include a low power consumption state different from a power-off state, and
- the defragmenting device rearranges the data such that a tile in which high access frequency data are collected and a tile in which low access frequency data are collected are present, and the defragmenting device rearranges the data based on a comparison result of an access frequency maximum value of one tile among tiles adjacent to each other in a number management and an access frequency minimum value of an other tile.
A method comprising:
- for a memory including a plurality of pages on each of which data can be arranged, rearranging the data arranged on the plurality of pages, wherein the memory includes a plurality of tiles each including one or more pages, each of the plurality of tiles is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different, and the plurality of states include a low power consumption state different from a power-off state;
- rearranging the data such that a tile in which high access frequency data are collected and a tile in which low access frequency data are collected are present;
- and
- rearranging the data based on a comparison result of an access frequency maximum value of one tile among tiles adjacent to each other in a number management and an access frequency minimum value of an other tile.
A non-transitory computer readable medium storing a program, the program being executable by at least one processor to perform operations comprising:
- for a memory including a plurality of pages on each of which data can be arranged, rearranging the data arranged on the plurality of pages, wherein the memory includes a plurality of tiles each including one or more pages, each of the plurality of tiles is configured to be capable of transitioning among a plurality of states in which power consumption suppression rates are different, and the plurality of states include a low power consumption state different from a power-off state;
- rearranging the data such that a tile in which high access frequency data are collected and a tile in which low access frequency data are collected are present;
- and
- rearranging the data based on a comparison result of an access frequency maximum value of one tile among tiles adjacent to each other in a number management and an access frequency minimum value of an other tile.
Dependencies are inferred from the claim text.