Semiconductor integrated circuit, a method for testing the semiconductor integrated circuit, and a semiconductor system

A semiconductor integrated circuit configured to receive a test scan input signal, a test clock signal, and a test mode signal and to output a secure scan output signal, the semiconductor integrated circuit comprising:

• a secure key circuit comprising N delay circuits and N flip-flops, wherein the N delay circuits are configured to receive the test scan input signal and to output N delay input signals, each of which having a different delay with respect to the test scan input signal and the N flip-flops are configured to latch logic values of the N delay input signals at each rising edge of the test clock signal and to output an input key signal including the latched logic values, such that an input key of the input key signal is varied at each rising edge of the test clock signal;
• a key comparator configured to output a verification result signal indicating whether the input key is identical with a reference key;
• a chip configured to generate a scan output signal based on the test scan input signal;
• a scan output remapper configured to receive the scan output signal, to output an unobfuscated scan output signal as the secure scan output signal based on the verification result signal indicating that the input key of the input key signal is identical with the reference key, to obfuscate the scan output signal based on the verification result signal indicating that the input key of the input key signal is different from the reference key, and to output the obfuscated scan output signal as the secure scan output signal;
• and
• a secure scan controller configured to control the secure key circuit, the key comparator, the chip, and the scan output remapper,
• wherein Nis an integer that is greater than or equal to 1.