FUSI gated device formation

A method for forming an integrated chip, comprising:

• depositing a gate dielectric layer and a conductive layer over a substrate;
• depositing a polysilicon layer over the conductive layer;
• depositing a first dielectric layer on the polysilicon layer;
• performing a patterning process on the first dielectric layer and a middle region of the polysilicon layer;
• forming a silicide layer on the conductive layer, wherein a segment of the polysilicon layer abuts an outer sidewall of the silicide layer;
• etching the first dielectric layer and the polysilicon layer to form openings over the substrate;
• forming a pair of source/drain regions in the substrate on opposing sides of the silicide layer;
• and
• depositing a second dielectric layer lining the openings, wherein the second dielectric layer contacts first sidewalls of the first dielectric layer, first sidewalls of the polysilicon layer, and first sidewalls of the conductive layer.

An integrated chip, comprising:

• a gate dielectric structure over a substrate;
• a first conductive layer over the gate dielectric structure;
• a second conductive layer directly contacting a top surface of the first conductive layer;
• a pair of source/drain regions disposed in the substrate, wherein the second conductive layer is between the pair of source/drain regions;
• and
• a polysilicon layer contacting opposing sidewalls of the second conductive layer, wherein the polysilicon layer directly contacts the top surface of the first conductive layer, wherein a top surface of the polysilicon layer is above a top surface of the second conductive layer, wherein the polysilicon layer is disposed on opposing sides of each source/drain region in the pair of source/drain regions.