CMOS fabrication methods for back-gate transistor

A method comprising:

• forming an n-type transistor comprising:
• forming a first gate electrode;
• depositing a first gate dielectric layer over the first gate electrode;
• forming a first low-dimensional semiconductor layer comprising a first portion over the first gate dielectric layer;
• forming a dielectric doping layer comprising aluminum oxide or hafnium oxide over and contacting the first low-dimensional semiconductor layer;
• and
• performing an annealing process to drive aluminum or hafnium in the dielectric doping layer into the first low-dimensional semiconductor layer;
• forming a p-type transistor comprising:
• forming a second gate electrode;
• depositing a second gate dielectric layer over the second gate electrode;
• forming a second low-dimensional semiconductor layer comprising a second portion over the second gate dielectric layer;
• and
• forming a dielectric passivation layer over and contacting the second low-dimensional semiconductor layer, wherein the dielectric passivation layer and the dielectric doping layer are formed of different materials.

A method comprising:

• depositing a dielectric layer over a semiconductor substrate;
• depositing an isolation layer over the dielectric layer;
• forming a first work function layer over a first portion of the isolation layer, wherein the first work function layer is an n-type work function layer;
• forming a first low-dimensional semiconductor layer on a first top surface and a first sidewall of the first work function layer;
• forming first source/drain contacts contacting opposing end portions of the first low-dimensional semiconductor layer;
• forming a dielectric doping layer over and contacting a channel portion of the first low-dimensional semiconductor layer, wherein the dielectric doping layer comprises a metal selected from aluminum and hafnium;
• and
• performing an annealing process to diffuse the metal in the dielectric doping layer into the channel portion of the first low-dimensional semiconductor layer.