Memory cell and memory array select transistor

A semiconductor memory array comprising:

• a plurality of semiconductor devices configured to function as a memory select transistor with increased on-state drain current;
• wherein each of said semiconductor devices comprises:
• a substrate having a first conductivity type selected from p-type conductivity type and n-type conductivity type;
• a buried layer having a second conductivity type selected from said p-type conductivity type and said n-type conductivity type and being different from said first conductivity type;
• a body having said first conductivity type;
• a source region and a drain region each having said second conductivity type and being separated by said body;
• a gate positioned in between said source region and said drain region;
• a charge trap layer containing a substantial number of charge trap centers that may absorb excess majority carrier, said charge trap layer contacting at least one of said source region and said drain region;
• and
• an insulating layer comprising an STI contacting said charge trap layer;
• wherein said semiconductor device is configured to function as a select transistor for at least one memory element connected to said drain region or said source region, wherein a state of said at least one memory element is determined by a resistivity of said at least one memory element.