Semiconductor device and manufacturing method thereof
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsWei-Cheng Wu, Li-Feng Teng
Life of this patent
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Abstract
A semiconductor device includes a non-volatile memory. The non-volatile memory includes a first dielectric layer disposed on a substrate, a floating gate disposed on the dielectric layer, a control gate and a second dielectric layer disposed between the floating gate and the control gate. The second dielectric layer includes one of a silicon oxide layer, a silicon nitride layer, and a multi-layer thereof. The first dielectric layer includes a first-first dielectric layer formed on the substrate and a second-first dielectric layer formed on the first-first dielectric layer. The second-first dielectric layer includes a dielectric material having a dielectric constant higher than silicon nitride.
Claims20
A semiconductor device including a non-volatile memory, the non-volatile memory comprising:
- a first dielectric layer disposed on a substrate comprising a stepped surface;
- a floating gate disposed on the first dielectric layer;
- a control gate;
- a select gate;
- an erase gate;
- and
- a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon nitride layer, a silicon oxide layer, and a multi-layer thereof, wherein the first dielectric layer includes silicon oxide,
- wherein the first dielectric layer comprises a multi-layer structure including at least a first layer that extends below the select gate, and a second layer that does not extend below the select gate.
A semiconductor device, comprising:
- a substrate comprising a step formed between a memory cell area and a logic circuit area;
- a non-volatile memory formed in the memory cell area;
- and
- a logic circuit including a field effect transistor (FET) formed in the logic circuit area,
- wherein the non-volatile memory includes:
- a first dielectric layer disposed on a substrate;
- a floating gate disposed on the first dielectric layer;
- a control gate;
- a select gate;
- an erase gate;
- and
- a second dielectric layer disposed between the floating gate and the control gate, and having one of a silicon nitride layer, a silicon oxide layer, and a multi-layers thereof, wherein a gate dielectric layer of the FET includes a same material as the first dielectric layer,
- wherein the first dielectric layer comprises a multi-layer structure including at least a first layer that extends below the select gate, and a second layer that does not extend below the select gate.
A non-volatile memory comprising:
- an isolation insulating layer embedded in a semiconductor substrate and separating a memory cell area and a logic circuit area, wherein the semiconductor substrate comprises a step such that the memory cell area has a lower height than the logic circuit area;
- a first dielectric layer disposed on the semiconductor substrate;
- a floating gate disposed on the first dielectric layer;
- a control gate;
- an erase gate;
- a select gate;
- a second dielectric layer disposed between the floating gate and the control gate;
- and
- first to third sidewall spacers,
- wherein:
- the control gate, the erase gate, and the select gate include a conductive layer made of a same material,
- the erase gate and the select gate include a polysilicon layer under the conductive layer,
- the control gate includes no polysilicon layer, and
- the first dielectric layer comprises a multi-layer structure including at least a first layer that extends below the select gate, and a second layer that does not extend below the select gate.
Dependencies are inferred from the claim text.