# US 12,439,591 B2 · Memory device, integrated circuit and manufacturing method of the same > Agents: this data is available as JSON from the patentgrep API and MCP server — see https://patentgrep.com/llms.txt - Number: US 12,439,591 B2 - Document ID: US12439591B2 - Status: Granted - Kind: B2 - Application number: 18/403,730 - Filed: 2024-01-04 - Published: 2024-10-24 - Granted: 2025-10-07 - Earliest claimed: 2023-04-21 - Assignees: Ipcell Corporation Limited - Applicants: Ipcell Corporation Limited - Inventors: Te-Hsun Hsu - Web page: https://patentgrep.com/patent/US12439591B2 ## CPC - H10B 20/25: One-time programmable ROM [OTPROM] devices, e.g. using electrically-fusible links - G11C 17/16: using electrically-fusible links - G11C 17/18: Auxiliary circuits, e.g. for writing into memory - H10B: ELECTRONIC MEMORY DEVICES - G11C: STATIC STORES (semiconductor memory devices H10B) ## Abstract A memory device comprises a memory cell comprising first to third transistors and a fuse element. A control terminal and a first terminal of the first transistor are coupled to a write word line and a source line respectively. The second transistor has a control terminal coupled to a second terminal of the first transistor and a first terminal coupled to a bit line. A first terminal of the fuse element is coupled to the second terminal of the first transistor and the control terminal of the second transistor. A control terminal of the third transistor is coupled to a read word line. First and second terminals of the third transistor are coupled to the source line and a second terminal of the second transistor. The first transistor is turned on to form a write path and the second and third transistors form a read path. ## Claims ### Claim 1 A memory device comprising a one-time programmable non-volatile memory cell that comprises: a first transistor, a control terminal of the first transistor and a first terminal of the first transistor coupled to a write word line and a source line respectively; a second transistor that has a control terminal coupled to a second terminal of the first transistor and has a first terminal coupled to a bit line; a fuse element, wherein a first terminal of the fuse element is coupled to the second terminal of the first transistor and the control terminal of the second transistor; and a third transistor, wherein a control terminal of the third transistor is coupled to a read word line, a first terminal of the third transistor is coupled to the source line and a second terminal of the third transistor is coupled to a second terminal of the second transistor, wherein the first transistor is configured to be turned on to form a write path to the fuse element, and the second transistor and the third transistor are configured as a read path. ### Claim 2 (depends on 1) The memory device of claim 1, wherein the fuse element and the second transistor share a gate structure as the first terminal of the fuse element and the control terminal of the second transistor, wherein the gate structure is configured to receive a program voltage in a write operation. ### Claim 3 (depends on 2) The memory device of claim 2, wherein in a read operation, when the one-time programmable non-volatile memory cell stores a low logic value, the gate structure is in a floating state, and when the one-time programmable non-volatile memory cell stores a high logic value, the gate structure has a read bias. ### Claim 4 (depends on 1) The memory device of claim 1, wherein before a write operation of writing a low logic value, the first terminal of the fuse element is coupled to a program line, wherein in the write operation of writing the low logic value, the first transistor is configured be turned on in response to the write word line having a first voltage, and the fuse element is configured to be melted, in response to the program line having the first voltage, to be electrically disconnected with the program line. ### Claim 5 (depends on 4) The memory device of claim 4, wherein in a read operation of reading the low logic value, the control terminal of the second transistor is in a floating state. ### Claim 6 (depends on 4) The memory device of claim 4, wherein in a read operation before the write operation of writing the low logic value, the one-time programmable non-volatile memory cell stores a high logic value and the control terminal of the second transistor has the first voltage. ### Claim 7 (depends on 1) The memory device of claim 1, wherein in a read operation and a write operation, bulk voltages of the first transistor to the third transistor are the same and are a grounded voltage level, and the source line has the grounded voltage level. ### Claim 8 (depends on 7) The memory device of claim 7, wherein in the read operation, the read word line has a first voltage and the bit line has a second voltage smaller than the first voltage. ### Claim 9 An integrated circuit comprising: a first transistor comprising a first active area coupled to a source line and a second active area separated from the first active area in a first direction; and a fuse element and a second transistor that comprise a common gate structure extending along a second direction, wherein the common gate structure includes a first gate portion and a second gate portion, wherein the fuse element further comprises a first via and a second via that contact the first gate portion, wherein the first via is coupled to a first conductive segment and the second via is coupled to the second active area through a second conductive segment, wherein an area where the first via contacts the first gate portion is smaller than an area where the second via contacts the first gate portion. ### Claim 10 (depends on 9) The integrated circuit of claim 9, wherein the fuse element further comprises: a third via coupled between the first conductive segment and a conductive line and configured to receive a program voltage from the first conductive line for the fuse element, wherein an area where the third via contacts the first conductive segment is smaller than the area where the first via contacts the first gate portion. ### Claim 11 (depends on 10) The integrated circuit of claim 10, wherein the area where the third via contacts the first conductive segment is smaller than the area where the second via contacts the first gate portion. ### Claim 12 (depends on 11) The integrated circuit of claim 11, wherein the fuse element further comprises: a fourth via coupled between the second conductive segment and the second active area, wherein the area where the third via contacts the first conductive segment is smaller than an area where the fourth via contacts the second conductive segment. ### Claim 13 (depends on 9) The integrated circuit of claim 9, wherein the fuse element further comprises: a third via coupled between the second conductive segment and the second active area, wherein the area where the first via contacts the first gate portion is smaller than an area where the third via contacts the second conductive segment. ### Claim 14 (depends on 9) The integrated circuit of claim 9, wherein a width of the first gate portion along a second direction different from the first direction is greater than a width of the second gate portion. ### Claim 15 (depends on 9) The integrated circuit of claim 9, further comprising: a third transistor configured to form a read path with the second transistor and comprising a third active area coupled to the source line, wherein the third active area is separated from the first active area along the first direction. ### Claim 16 (depends on 15) The integrated circuit of claim 15, wherein the second transistor further comprises: a fourth active area coupled to the third transistor; and a fifth active area configured to receive a bit line voltage in a read operation. ### Claim 17 A manufacturing method of integrated circuit comprising the following steps: forming a first active region and a second active region that are separated from each other along a first direction in a substrate; forming a first gate structure extending along the first direction, wherein forming the first gate structure comprising: forming a first gate portion of the first gate structure on a shallow trench isolation and forming a second gate portion overlapping the first gate structure of the first active region in a layout view; and forming a first conductive structure and a second conductive structure that contact the first gate portion, the first conductive structure coupled to the second active region, wherein an area of the first conductive structure is larger than an area of the second conductive structure. ### Claim 18 (depends on 17) The manufacturing method of claim 17, further comprising: forming a first conductive segment that contacts the second conductive structure in a first semiconductor layer; forming a third conductive structure on the first conductive segment; and forming a conductive line that contacts the third conductive structure in a second semiconductor layer above the first semiconductor layer, wherein an area of the third conductive structure is smaller than the area of the second conductive structure. ### Claim 19 (depends on 18) The manufacturing method of claim 18, further comprising: forming a fourth conductive structure on the second active region, wherein the fourth conductive structure is coupled to the first conductive structure and an area of the fourth conductive structure is greater than the area of the third conductive structure, wherein the third conductive structure partially overlaps the first conductive segment in the layout view. ### Claim 20 (depends on 17) The manufacturing method of claim 17, further comprising: forming a second gate structure and a third gate structure that are separated from the first gate structure along a second direction, wherein the second gate structure overlaps the first active region in the layout view and receives a read word line voltage, and the third gate structure overlaps the second active region in the layout view and receives a write word line voltage.