Wide frequency range high speed clock multiplexer

A system, receiving an input signal and providing an output signal, the system comprising:

• a device comprising a first circuit and a second circuit, wherein the device is configured to:
• receive, by the first circuit, an input signal having a first frequency, the first circuit including a first node and a second node;
• receive, by the second circuit, an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node;
• and
• output, by the device, the output signal corresponding to the first frequency or the second frequency,
• wherein a first inductor is coupled between the first node of the first circuit and the first node of the second circuit, and
• wherein a second inductor is coupled between the second node of the first circuit and the second node of the second circuit, and
• operate a first transistor between the first node of the second circuit and the second node of the second circuit as a first switch that, upon activation responsive to a control signal corresponding to a high-speed path, operates in a closed state to electrically couple the first node of the second circuit and the second node of the second circuit, the first transistor coupled to a plurality of transistors that are electrically coupled between a power source and a drain or source node of the first transistor and operate in the closed state with the first transistor in the high-speed path.

A method of controlling a device, the method comprising:

• receiving, by a first circuit, an input signal having a first frequency, the first circuit including a first node and a second node;
• receiving, by a second circuit, an input signal having a second frequency different from the first frequency, the second circuit including a first node and a second node;
• and
• outputting, by the device, an output signal corresponding to the first frequency or the second frequency,
• wherein a first inductor is coupled between the first node of the first circuit and the first node of the second circuit, wherein a second inductor is coupled between the second node of the first circuit and the second node of the second circuit;
• and
• operating a first transistor between the first node of the second circuit and the second node of the second circuit as a first switch that, upon activation responsive to a control signal corresponding to a high-speed path, operates in a closed state to electrically couple the first node of the second circuit and the second node of the second circuit, the first transistor coupled to a plurality of transistors that are electrically coupled between a power source and a drain or source node of the first transistor and operate in the closed state with the first transistor in the high-speed path.