Chip package structure with redistribution layer having bonding portion

A chip package structure, comprising:

• a first redistribution layer having a bonding portion, wherein the bonding portion comprises a first dielectric layer and a first conductive pad in the first dielectric layer;
• a chip structure bonded to the bonding portion, wherein the chip structure comprises a semiconductor substrate, a second dielectric layer and a second conductive pad in the second dielectric layer, the second dielectric layer is between and in direct contact with the first dielectric layer and the semiconductor substrate, and the first conductive pad is in direct contact with the second conductive pad;
• a protective layer over the first redistribution layer and surrounding the chip structure, wherein a first portion of the protective layer extends into the first redistribution layer and surrounds the bonding portion;
• and
• a conductive via structure passing through the first portion of the protective layer and penetrating into the first dielectric layer, wherein the first portion of the protective layer is between the conductive via structure and the bonding portion, and
• the chip structure comprises:
• the semiconductor substrate;
• and
• a second redistribution layer under the semiconductor substrate, wherein the second redistribution layer has a second bonding portion and a second portion between the second bonding portion and the semiconductor substrate, the second bonding portion is narrower than the second portion, and the second bonding portion is in direct contact with the bonding portion.

A chip package structure, comprising:

• a redistribution layer having a bonding portion, wherein the bonding portion has a first top surface;
• a chip structure bonded to the first top surface of the bonding portion;
• a protective layer over the redistribution layer and surrounding the chip structure, wherein a portion of the protective layer extends into the redistribution layer and surrounds the bonding portion, and a line width of the portion is less than a first width of the bonding portion;
• and
• a conductive via structure passing through the portion of the protective layer, wherein the portion of the protective layer separates the conductive via structure from the bonding portion, a bottom surface of the conductive via structure is lower than the first top surface, and
• the chip structure comprises:
• the semiconductor substrate;
• and
• a second redistribution layer under the semiconductor substrate, wherein the second redistribution layer has a second bonding portion and a second portion between the second bonding portion and the semiconductor substrate, the second bonding portion is narrower than the second portion, and the second bonding portion is in direct contact with the bonding portion.