High throughput additive manufacturing for integrated circuit components containing traces with feature size and grain boundaries

A method comprising:

• depositing one or more sacrificial dielectric traces on a substrate for an integrated circuit component;
• depositing a conductive layer on the one or more sacrificial dielectric traces using cold spray;
• planarizing the conductive layer to expose the one or more sacrificial dielectric traces;
• and
• removing the one or more sacrificial dielectric traces without removing the conductive layer,
• wherein the conductive layer forms one or more conductive traces for the integrated circuit component.

An integrated circuit component comprising:

• a substrate;
• and
• one or more conductive traces on the substrate,
• wherein individual conductive traces of the one or more conductive traces have a feature size less than 50 micrometers,
• wherein individual conductive traces of the one or more conductive traces have a thickness of at least 50 micrometers,
• wherein void spaces are defined between individual conductive traces of the one or more conductive traces.