Chip package and method of manufacturing the same

A chip package, comprising:

• a redistribution layer, comprising;
• an insulation part, having a first surface, a second surface opposite to the first surface, and a side surface located between the first surface and the second surface;
• an outer wiring layer, located at the insulation part, wherein an outer surface of the outer wiring layer and the second surface are coplanar, and the side surface extends from the first surface to the second surface;
• a plurality of first pads, located at the first surface;
• a plurality of second pads, located at the second surface;
• a chip, disposed on the first surface and electrically connected to the first pads;
• and
• an encapsulation member, wrapping the chip and the redistribution layer, and completely covering the first surface and the side surface, wherein the encapsulation member exposes the second pads, and the encapsulation member is not flush with the first surface and the side surface,
• wherein the encapsulation member is made of an electrical insulating material,
• wherein the encapsulation member is in direct contact with the first surface and exposes the first pads.