Operation method of memory, memory and memory system
AssigneeYangtze Memory Technologies Co., Ltd.
InventorsZhefan Li, Xiaodong Mei, Huangpeng Zhang, Yu Wang
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Abstract
Examples of the present application provide operation methods of memories, memory devices and systems. In an example, an operation method includes: in response to a first defective memory cell row of a plurality of memory cell rows in the memory being repaired before packaging, invalidating, in a post-package repair mode, a first repair strategy for repairing the first defective memory cell row before packaging, and configuring a second repair strategy for repairing the first defective memory cell row and storing the second repair strategy.
Claims20
An operation method of a memory performed in a post-package repair (PPR) mode, wherein the method comprises:
- determining that a first defective memory cell row of a plurality of memory cell rows in the memory was repaired pre-packaging before based on a first repair strategy for repairing the first defective memory cell row before packaging the memory to an electronic device;
- in response to the determination that the first defective memory cell row was repaired pre-packaging, setting a first control bit to a first preset value indicating that the first repair strategy is invalid;
- configuring a second repair strategy for repairing the first defective memory cell row by setting a second control bit to a second preset value indicating that the second repair strategy is valid;
- and
- storing the second repair strategy to the memory.
A memory, comprising:
- a memory array comprising a plurality of memory cell rows;
- a peripheral circuit coupled to the memory array and configured to:
- determine that a first defective memory cell row of a plurality of memory cell rows in the memory was repaired pre-packaging based on a first repair strategy for repairing the first defective memory cell row before packaging the memory to an electronic device;
- in response to determining that the first defective memory cell row was repaired pre-packaging, set, in a post-package repair (PPR) mode, a first control bit to a first preset value indicating that the first repair strategy is invalid;
- and
- configure a second repair strategy for repairing the first defective memory cell and store the second repair strategy by setting a second control bit to a second preset value indicating that the second repair strategy is valid.
A memory system, comprising:
- one or more memories, each comprising:
- a memory array comprising a plurality of memory cell rows;
- a peripheral circuit coupled to the memory array and configured to:
- determine that a first defective memory cell row of a plurality of memory cell rows in the memory was repaired pre-packaging based on a first repair strategy for repairing the first defective memory cell row before packaging the memory to an electronic device;
- in response to determining that the first defective memory cell row was repaired pre-packaging, set, in a post-package repair (PPR) mode, a first control bit to a first preset value indicating that the first repair strategy is invalid;
- and
- configure a second repair strategy for repairing the first defective memory cell and store the second repair strategy by setting a second control bit to a second preset value indicating that the second repair strategy is valid;
- and
- a memory controller coupled to the memories and configured to control the memories.
Dependencies are inferred from the claim text.