Memory device performing multiplication using logical states of memory cells
AssigneeMicron Technology, Inc.
InventorHernan Castro
Life of this patent
Estimating the term…
Abstract
Systems, methods, and apparatus related to memory devices that perform multiplication using logical states of memory cells. In one approach, a memory cell array has memory cells programmed to store weights for performing the multiplication. Voltages are applied to the memory cells. Each voltage represents one or more input bits to be multiplied by one of the weights. Output currents from the memory cells are accumulated in a common bitline. A sum of the output currents is digitized to provide a digital result. The digital results from several bitlines can be shifted based on bit significance and added to provide a final accumulation result from the multiplication.
Claims20
An apparatus comprising:
- a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
- voltage drivers configured to apply respective voltages to the memory cells, wherein each respective voltage represents a one-bit input, and wherein the voltages are applied so that the memory cells do not threshold;
- a first line coupled to first memory cells storing a respective bit of a first significance, wherein the first line is configured to sum first output currents from each of the first memory cells;
- a second line coupled to second memory cells storing a respective bit of a second significance, wherein the second significance is less than the first significance, and the second line is configured to sum second output currents from each of the second memory cells;
- and
- a logic circuit configured to provide an accumulation result based on the summed first output currents and the summed second output currents.
An apparatus comprising:
- a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
- and
- a multiplier-accumulator unit configured to perform a multiplication of the multi-bit weight by a multi-bit input and provide an accumulation result, wherein:
- the memory cells are kept in a sub-threshold mode during the multiplication;
- each bit of the multi-bit input is applied to the multiplier-accumulator unit at a respective time instance to obtain a respective result, wherein the respective result is based on summing output currents from the memory cells;
- and
- the accumulation result is based on the respective results obtained from applying the bits of the multi-bit input.
An apparatus comprising:
- a memory cell array comprising memory cells, wherein each memory cell is programmable to store a respective bit for a multi-bit weight, and each memory cell has a position in the array corresponding to a significance of its stored respective bit;
- voltage drivers configured to apply voltage pulses to the memory cells, wherein a respective width of each pulse represents a multi-bit input;
- a first line coupled to first memory cells storing a bit of a first significance, wherein the first line is configured to collect first output currents from each of the first memory cells for accumulating a first charge;
- a second line coupled to second memory cells storing a bit of a second significance, wherein the second significance is less than the first significance, and the second line is configured to collect second output currents from each of the second memory cells for accumulating a second charge;
- and
- a logic circuit configured to output a result based on the accumulated first charge and the accumulated second charge.
Dependencies are inferred from the claim text.