Code inspection method under weak memory ordering architecture and corresponding device

A computer device, comprising a processor, a memory, and a computer-readable storage medium storing a computer program, wherein the processor is coupled to the computer-readable storage medium, and when the computer program is executed by the processor, the processor is caused to perform operations:

• obtaining a first source code and a test code, wherein the first source code comprises a blocking mark, the test code indicates a condition that needs to be met for correct running of the first source code, the first source code corresponds to a plurality of threads, the plurality of threads have at least one shared memory, and the blocking mark indicates a location of a busy-wait loop in the first source code;
• generating, based on the first source code and the condition indicated by the test code, a plurality of execution flows under a weak memory ordering architecture for the plurality of threads that operate a same shared memory, wherein each execution flow is a code execution process in which a processor runs the plurality of threads to perform a read operation and/or write operation on the same shared memory, and a busy-wait loop exists in a target execution flow that comprises the blocking mark and that is in the plurality of execution flows;
• and
• determining the busy-wait loop in the target execution flow as an infinite loop if a read operation executed by a target thread in one iteration of the busy-wait loop cannot reference an unreferenced write operation when the plurality of threads are invoked to execute the busy-wait loop in the target execution flow, wherein the infinite loop indicates that an error exists in the first source code, and the target thread is any one of the plurality of threads.