Non-linear polar material based low power multiplier with transmission-gate based reset mechanism

An apparatus comprising:

• an AND gate comprising a majority gate or a minority gate having non-linear polar material, wherein the AND gate is to receive a multiplier and a multiplicand;
• a 1-bit full adder comprising a majority gate or a minority gate coupled to the AND gate, wherein the 1-bit full adder comprises non-linear polar material, and wherein the 1-bit full adder is to receive a sum input and a carry input;
• and
• a reset mechanism to reset nodes coupled to the non-linear polar material, wherein the reset mechanism is to apply a predetermined input to the multiplier, the multiplicand, the sum input, and the carry input during a reset phase, and to sequentially pull-up and pull-down the nodes during the reset phase, and to allow the nodes to float during an evaluation phase, and
• wherein the reset mechanism includes:
• a first transmission gate at an output of the AND gate;
• a second transmission gate at an output of a 3-input majority gate of the 1-bit full adder;
• and
• a third transmission gate at an output of a 5-input majority gate of the 1-bit full adder.

A system comprising:

• a processor circuitry to execute one or more instructions;
• a communication interface communicatively coupled to the processor circuitry;
• and
• a memory coupled to the processor circuitry, wherein the processor circuitry comprises a multiplier circuitry which includes:
• a majority gate or a minority gate having non-linear polar material, wherein the majority gate or the minority gate is coupled to a transmission gate;
• and
• a reset mechanism to reset a set of nodes coupled to the non-linear polar material during a reset phase separate from an evaluation phase, wherein a node from the set of nodes is coupled to the transmission gate, wherein the transmission gate is controllable by the reset mechanism, and wherein the reset mechanism is to sequence a pull-up event and a pull-down event according to logic condition of inputs to the majority gate or the minority gate.