US 12,436,558 B2Granted

Hybrid clocking scheme for SERDES physical layer circuits

AssigneeQUALCOMM Incorporated

InventorsNitz Saputra, Sameer Wadhwa

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Abstract

A first inverter in a clock generation circuit is coupled to an input clock signal and has multiple driver slices. Each driver slice includes first transistors that have gates coupled to the input clock signal, second transistors that have sources coupled to rails of a power supply. Each of the second transistors has a drain coupled to a source of one of the first transistors. The second transistors are turned on or turned off based on signaling state of a differential enable signal. A tuning resistor is coupled to the drains of the first transistors and further coupled to an output of the first inverter. A second inverter outputs a quadrature version of the input clock signal and has an input coupled to the output of the first inverter. A first tunable capacitor is coupled to the output of the first inverter.

A clock generation circuit, comprising:

a first inverter coupled to an input clock signal and comprising driver slices, each driver slice in the first inverter comprising:
a first pair of transistors that have gates that are coupled to the input clock signal;
a second pair of transistors that includes a first transistor that has a source coupled to a higher voltage rail of a power supply and a drain coupled to a source of a first transistor in the first pair of transistors, and a second transistor that has a source coupled to a lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the first pair of transistors, wherein the second pair of transistors is turned on when a first differential enable signal is in a first signaling state and turned off when the first differential enable signal is in a second signaling state;
and
a first tuning resistor coupled to the drains of the first pair of transistors and further coupled to an output of the first inverter;
a first tunable capacitor coupled to the output of the first inverter;
and
a second inverter that has an input coupled to the output of the first inverter and that outputs a quadrature version of the input clock signal, wherein the second inverter comprises
a third pair of transistors that have gates that are coupled to the output of the first inverter;
a fourth pair of transistors that includes a first transistor that has a source coupled to the higher voltage rail of the power supply and a drain coupled to a source of a first transistor in the third pair of transistors, and a second transistor that has a source coupled to the lower voltage rail of the power supply and a drain coupled to a source of a second transistor in the third pair of transistors, wherein the fourth pair of transistors is turned on when a second differential enable signal is in the first signaling state and turned off when the second differential enable signal is in the second signaling state;
a second tuning resistor coupled to the drains of the third pair of transistors and to an output of the second inverter;
and
a second tunable capacitor coupled to the output of the second inverter.

10 more elements

Facts

Application

18/509,643Filed 15 Nov 2023

Published

US 2025/0155917 A115 May 2025

Granted

7 Oct 2025

Term ends

Not estimatedThe source records don’t support an estimate.

Classification8 codes

G06F 1/08
Generating or distributing clock signals or signals derived directly therefrom: clock generators with changeable or programmable clock frequency
H03K 5/131
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: digitally controlled
H03K 5/134
Using a chain of active delay devices: with field-effect transistors
H03K 5/135
Arrangements having a single output and transforming input signals into pulses delivered at desired time intervals: by the use of time reference…

Abstract

Claims9