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US 12,433,056 B2Granted
Planar germanium photodetector
AssigneeIntel Corporation
InventorsWei Qian, Zhi Li
Life of this patent
Estimating the term…
Abstract
Embodiments described herein may be related to apparatuses, processes, and techniques directed to a planar germanium photodetector that includes n-type and p-type amorphous silicon deposits on a germanium slab. During operation, a uniform electrical field is formed across the germanium bulk between the amorphous silicon deposits. Other embodiments may be described and/or claimed.
Claims25
A photodetector comprising:
- a substrate;
- a germanium layer on top of the substrate;
- and
- an n-type silicon layer at least partially within the germanium layer and a p-type silicon layer at least partially within the germanium layer, wherein a portion of the germanium layer between the n-type silicon layer and the p-type silicon layer isolates the n-type silicon layer and the p-type silicon layer from each other, the n-type silicon layer having an uppermost surface at a same level as an uppermost surface of the germanium layer, and the p-type silicon layer having an uppermost surface at a same level as the uppermost surface of the germanium layer.
1 more element
A method comprising:
- providing a layer that includes silicon;
- forming a layer that includes germanium on a side of the layer that includes silicon;
- forming an n-type layer of silicon within the layer that includes germanium, the n-type layer of silicon having an uppermost surface at a same level as an uppermost surface of the layer that incudes germanium;
- and
- forming a p-type layer of silicon within the layer that includes germanium, the p-type layer of silicon having an uppermost surface at a same level as the uppermost surface of the layer that includes germanium, wherein a portion of the layer that includes germanium isolates the n-type layer of silicon and the p-type layer of silicon.
2 more elements
A package comprising:
- a photodetector comprising:
- a silicon substrate;
- a germanium layer on top of the silicon substrate;
- an n-type amorphous silicon layer at least partially within the germanium layer and a p-type amorphous silicon layer at least partially within the germanium layer, wherein a portion of the germanium layer between the n-type amorphous silicon layer and the p-type amorphous silicon layer isolates the n-type amorphous silicon layer and the p-type amorphous silicon layer from each other, the n-type silicon layer having an uppermost surface at a same level as an uppermost surface of the germanium layer, and the p-type silicon layer having an uppermost surface at a same level as the uppermost surface of the germanium layer, and wherein the n-type amorphous silicon layer and the p-type amorphous silicon layer are within a plane;
- a first electrical contact electrically coupled with the n-type amorphous silicon layer;
- and
- a second electrical contact electrically coupled with the p-type amorphous silicon layer;
- and
- an electrical component electrically coupled with the first electrical contact and the second electrical contact.
6 more elements
Dependencies are inferred from the claim text.