US 12,433,007 B2Granted

Transistor gate trench engineering to decrease capacitance and resistance

AssigneeIntel Corporation

InventorsSeung Hoon Sung, Willy Rachmady, Jack T. Kavalieros, Han Wui Then, Marko Radosavljevic

Life of this patent

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Abstract

Techniques are disclosed for transistor gate trench engineering to decrease capacitance and resistance. Sidewall spacers, sometimes referred to as gate spacers, or more generally, spacers, may be formed on either side of a transistor gate to help lower the gate-source/drain capacitance. Such spacers can define a gate trench after dummy gate materials are removed from between the spacers to form the gate trench region during a replacement gate process, for example. In some cases, to reduce resistance inside the gate trench region, techniques can be performed to form a multilayer gate or gate electrode, where the multilayer gate includes a first metal and a second metal above the first metal, where the second metal includes lower electrical resistivity properties than the first metal. In some cases, to reduce capacitance inside a transistor gate trench, techniques can be performed to form low-k dielectric material on the gate trench sidewalls.

Claims19

Dependent claims

An integrated circuit comprising:

a gate electrode having a first portion and a second portion;
a first spacer and a second spacer, the gate electrode laterally between the first and second spacers;
a body at least below the gate electrode and comprising semiconductor material;
a source region and a drain region, the body at least partially between the source and drain regions;
first and second dielectric materials that have different dielectric constants,
wherein the first dielectric material is laterally present at least between the first portion of the gate electrode and the first spacer and vertically between the body and the first portion of the gate electrode such that a bottom surface of the first portion of the gate electrode is vertically overlapping with the first dielectric material, without the second dielectric material being laterally present between the first portion of the gate electrode and the first spacer, and
wherein the second dielectric material is laterally present at least between the second portion of the gate electrode and the first spacer, without the first dielectric material being laterally present between the second portion of the gate electrode and the first spacer, wherein the second dielectric material has an outermost sidewall in vertical alignment with an outermost sidewall of the first dielectric material;
and
a source or drain contact on the source region or the drain region, the source or drain contact laterally adjacent to the first spacer or the second spacer, respectively.

6 more elements

Dependencies are inferred from the claim text.

Facts

Application: 16/990,219Filed 11 Aug 2020 · continuation
Published: US 2020/0373403 A126 Nov 2020
Granted: 30 Sep 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification14 codes

H10D 64/671
Electrodes having a conductor capacitively coupled to a semiconductor by an insulator, e.g. MIS electrodes: the conductor having lateral variation…
H10D 30/0273
Of lateral single-gate IGFETs: forming final gates or dummy gates after forming source and drain electrodes, e.g. contact first technology
H10D 30/60
Field-effect transistors [FET]: insulated-gate field-effect transistors [IGFET]
H10D 64/01324
Characterised by the conductor: characterised by the sectional shape, e.g. T or inverted-T

Family

PCT/US2016/025597Parent of this continuation · filed 1 Apr 2016
US 2020/0373403 A1Pre-grant publication · published 26 Nov 2020
Application16/080,824Parent of this continuation
US 10,784,360 B2Parent of this continuation
US 2019/0088759 A1Published application
US 12,433,007 B2This patent

From the US filing history. Foreign family members aren’t listed.