2D-channel transistor structure with asymmetric substrate contacts

A semiconductor structure comprising:

• a first dielectric film on a semiconductor substrate;
• a metal feature embedded in the first dielectric film;
• a second dielectric film on the first dielectric film and the metal feature;
• a via feature embedded in the second dielectric film and landing on the metal feature;
• a channel layer of 2-dimensional (2D) material or carbon nanotube (CNT) disposed on the second dielectric film;
• a gate stack disposed on the channel layer;
• and
• a source contact and a drain contact disposed on both sides of the gate stack and landing on the channel layer, wherein
• the channel layer is inserted between the source contact and the via feature,
• the source contact overlaps with the via feature and the metal feature in a top view,
• the drain contact is distanced away from the via feature in the top view, and
• the source contact is isolated from the semiconductor substrate by the first dielectric film.

A semiconductor structure comprising:

• a first dielectric layer on a semiconductor substrate;
• a conductive feature on the first dielectric layer;
• a second dielectric layer on the conductive feature such that the conductive feature is sandwiched between the first and second dielectric layer;
• a via feature embedded in the second dielectric layer;
• a channel layer of 2-dimensional (2D) material or carbon nanotube (CNT) disposed on the second dielectric layer;
• a gate stack disposed on the channel layer;
• and
• a source contact and a drain contact disposed on both sides of the gate stack, wherein the channel layer is inserted between the via feature and the source contact, wherein the conductive feature is electrically connected to the conductive feature through the channel layer and the via feature, and wherein the drain contact extends to the channel layer and is isolated from the conductive feature by the second dielectric layer.