Back-gate effect control via doping

A silicon on insulator (SOI) structure, comprising:

• an RF-SOI substrate, the RF-SOI substrate comprising
• a high resistivity silicon (HR-Si) substrate;
• a trap-rich layer overlying the HR-Si substrate;
• a buried oxide (BOX) layer overlying the trap-rich layer;
• and
• a thin silicon layer overlying the BOX layer;
• a first circuit formed in a first silicon region of the thin silicon layer;
• and
• a first implant in a region of the trap-rich layer that is immediately below the first circuit,
• wherein:
• the first implant is configured to be biased with a first voltage that is based on an operating state of the first circuit;
• the SOI structure further comprises a second implant in a region of the trap-rich layer disposed about the first implant;
• an interface between the first implant and the second implant forms a first junction;
• and
• the first junction is fully contained in the trap-rich layer and separated from the HR-Si substrate by an undoped region of the trap-rich layer.

A silicon on insulator (SOI) structure, comprising:

• an RF-SOI substrate, the RF-SOI substrate comprising
• a high resistivity silicon (HR-Si) substrate;
• a trap-rich layer overlying the HR-Si substrate;
• a buried oxide (BOX) layer overlying the trap-rich layer;
• and
• a thin silicon layer overlying the BOX layer;
• a first circuit formed in a first silicon region of the thin silicon layer;
• and
• a first implant in a region of the trap-rich layer that is immediately below the first circuit,
• wherein
• the first implant is configured to be biased with a first voltage that is based on an operating state of the first circuit,
• the SOI structure further comprises
• a second implant in a region of the trap-rich layer that surrounds the first implant;
• a second circuit formed in a second silicon region of the thin silicon layer, the second silicon region isolated from the first silicon region;
• and
• a third implant in a region of the trap-rich layer that is immediately below the second circuit, the third implant separated from the first implant by an undoped region of the trap-rich layer,
• the third implant is configured to be biased with a third voltage that is based on an operating state of the second circuit, the SOI structure further comprises a fourth implant in a region of the trap-rich layer that surrounds the third implant,
• an interface between the first implant and the second implant forms a first junction, and
• an interface between the third implant and the fourth implant forms a second junction.