US 12,431,997 B2Granted

Multiplexer and serializer including the same

AssigneeSamsung Electronics Co., Ltd.

InventorsJaehyeok Baek, Daehyun Kwon, Saetbyeol Kim, Hye-Ran Kim

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Abstract

A multiplexer selects one of a first to a fourth data signal in response to a first to a fourth pulse. The first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle. The multiplexer includes: (1) a NAND gate that receives the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse and outputs a first gate signal and (2) a NOR gate that receives the first data signal, the fourth complementary data signal, and a first complementary pulse that is complementary to the first pulse and outputs a second gate signal. The first data signal corresponds to a rising edge of the first pulse, and the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

Claims20

Dependent claims

A multiplexer that selects one of a first to a fourth data signal in response to a first to a fourth pulse, the first to fourth pulses respectively correspond to the first to fourth data signals and sequentially toggle, the multiplexer comprising:

a NAND gate configured to output a first gate signal in response to receiving the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse;
a NOR gate configured to output a second gate signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse;
a first transistor including a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected with an output terminal of the multiplexer;
and
a second transistor including a first terminal connected with the output terminal of the multiplexer, a gate that receives the second gate signal, and a second terminal to which a ground voltage is applied, wherein:
the first data signal corresponds to a rising edge of the first pulse, and
the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

4 more elements

A serializer comprising:

a clock multiplexer configured to generate first to fourth pulses based on first to fourth clocks, wherein the first to fourth clocks have a phase difference of 90 degrees with each other and the first to fourth pulses toggle sequentially;
and
a multiplexer configured to output an output signal, which is based on a first to a fourth data signal, in response to the first to fourth pulses and first to fourth complementary pulses respectively complementary to the first to fourth pulses, wherein:
the first to fourth data signals correspond to the first to fourth pulses, respectively,
the multiplexer includes:
a NAND gate configured to output a first gate signal in response to receiving the first data signal, a fourth complementary data signal complementary to the fourth data signal, and the first pulse;
and
a NOR gate configured to output a second gate signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse, and
a level of the output signal is based on the first gate signal and the second gate signal.

6 more elements

A serializer comprising:

a clock multiplexer configured to generate first to fourth pulses based on first to fourth clocks, wherein the first to fourth clocks have a phase difference of 90 degrees with each other and the first to fourth pulses toggle sequentially;
and
a multiplexer configured to output an output signal, which is based on a first to a fourth data signal, in response to the first to fourth pulses and first to fourth complementary pulses respectively complementary to the first to fourth pulses, wherein:
the first to fourth data signals correspond to the first to fourth pulses, respectively, the multiplexer includes:
a NAND gate configured to output a first gate signal in response to receiving the first data signal, a fourth complementary data signal that is a complementary signal of the fourth data signal, and the first pulse;
a NOR gate configured to output a second gate signal in response to receiving the first data signal, the fourth complementary data signal, and a first complementary pulse complementary to the first pulse;
a first transistor including a first terminal to which a first power supply voltage is applied, a gate that receives the first gate signal, and a second terminal connected with an output terminal of the multiplexer;
and
a second transistor including a first terminal connected with the output terminal of the multiplexer, a gate that receives the second gate signal, and a second terminal to which a ground voltage is applied,
the first data signal corresponds to a rising edge of the first pulse, and
the fourth complementary data signal corresponds to a rising edge of the fourth pulse.

8 more elements

Dependencies are inferred from the claim text.

Facts

Application: 17/680,787Filed 25 Feb 2022
Priority: KR 10-2021-00877605 Jul 2021
Published: US 2023/0006750 A15 Jan 2023
Granted: 30 Sep 2025
Term ends: Not estimatedThe source records don’t support an estimate.

Classification9 codes

H04J 3/04
Details: distributors combined with modulators or demodulators
H03K 17/6872
The output circuit comprising more than one controlled field-effect transistor: using complementary field-effect transistors
H03K 19/0948
Using MOSFET or insulated gate field-effect transistors, i.e. IGFET: using CMOS or complementary insulated gate field-effect transistors
H03K 19/1737
Controllable logic circuits: using multiplexers