Duty-cycle matched differential clock divider circuit

A method for generating differential frequency divided clock signals, the method comprising:

• generating complementary input clock signals, comprising a positive clock signal and a negative clock signal;
• receiving, by a primary latch including a single data input terminal and a single data output terminal, a feedback signal at the single data input terminal and the complementary input clock signals;
• producing, by the primary latch, a first output signal at the single data output terminal;
• receiving, by a differential latch, the first output signal and the complementary input clock signals;
• producing, by the differential latch, a second output signal and a third output signal;
• inverting the second output signal to produce the feedback signal applied to the single data input terminal of the primary latch;
• and
• inverting the second output signal and the third output signal to generate differential frequency divided clock signals.