Freeze and clear logic circuits and methods for integrated circuits

A method for controlling an output signal of a first logic circuit in an integrated circuit, the method comprising:

• driving the output signal of the first logic circuit to a predefined logic state with freeze circuitry in response to a freeze signal being asserted during power-up of the integrated circuit;
• controlling the output signal of the first logic circuit based on a first output signal of a programmable logic circuit after the power-up of the integrated circuit in response to the freeze signal being de-asserted;
• asserting a control signal with clear logic circuitry in response to a clear signal after the power-up of the integrated circuit;
• and
• driving the output signal of the first logic circuit to the predefined logic state with the freeze circuitry in response to the control signal being asserted.

An integrated circuit comprising:

• a programmable logic circuit;
• freeze circuitry coupled to receive a freeze signal and a control signal;
• a first logic circuit coupled to receive a first output signal of the programmable logic circuit, wherein the first logic circuit is coupled to receive an output signal of the freeze circuitry, and wherein the freeze circuitry causes an output signal of the first logic circuit to be in a predefined logic state in response to the freeze signal being asserted during power-up of the integrated circuit;
• and
• clear circuitry that asserts the control signal in response to a clear signal being asserted after the power-up of the integrated circuit, wherein the freeze circuitry causes the output signal of the first logic circuit to be in the predefined logic state in response to the control signal being asserted.