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US 12,431,890 B2Granted
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals
AssigneepSemi Corporation
InventorsTero Tapio Ranta, Shawn Bawell, Robert W. Greene, Christopher N. Brindle, Robert Mark Englekirk
Life of this patent
Estimating the term…
Abstract
Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals are described. Such devices and method include use of symmetrical compensation capacitances, symmetrical series capacitors, or symmetrical sizing of the elements of the stack.
Claims19
An integrated circuit comprising:
- a series arrangement of three or more field-effect transistors (FET);
- wherein:
- i) the three or more FETs are configured to:
- a) be connected in series with a series arrangement of one or more capacitive elements
- b) receive a control signal to enable or disable the FETs thereby adjusting the capacitance between the two nodes,
- ii) compensation capacitive elements are coupled across at least one of the three or more FETs, and
- iii) a combination of the one or more capacitive elements and the three or more FETs is coupled between a first node and a second node.
4 more elements
An integrated circuit comprising:
- a series arrangement of two or more field-effect transistors (FET), wherein:
- i) the two or more FETs are configured to be connected in series with a series arrangement of one or more capacitive elements to couple a combination of the one or more capacitive elements and the two or more FETs between a first node and a second node;
- ii) each of the two or more FETs has a control node configured to receive a control signal via a resistive element to enable or disable the two or more FETs, and thereby adjusting the capacitance between the first node and the second node;
- and
- iii) compensation capacitive elements are coupled across at least one of the two or more FETs.
2 more elements
An integrated circuit comprising:
- a series arrangement of one or more capacitive elements;
- a series arrangement of a plurality of field-effect transistors (FET);
- and
- a compensation capacitive element,
- wherein:
- the one or more capacitive elements are in series with the plurality of FETs;
- a combination of the one or more capacitive elements and the plurality of FETs is coupled between a first node and a second node;
- the plurality of FETs are configured to receive a control signal to enable or disable the FETs, thereby adjusting the capacitance between the two nodes, and
- the compensation capacitive element is connected across one or more FETs of the plurality of FETs.
6 more elements
Dependencies are inferred from the claim text.