Data communication link with capacitor-based pumped output

A serial data link output driver having serial data input and serial data output terminals, the serial data link output driver comprising:

• an input logic circuit having at least one input terminal coupled to the serial data link output driver input terminal for receiving serial data signal therefrom;
• a capacitor pump circuit including at least one pair of capacitors, each capacitor of the at least one pair of capacitors having at least one first terminal coupled to a corresponding output terminal of the input logic circuit for establishing a reference voltage for each capacitor;
• a first output drive circuit including at least a first P channel output transistor having a gate terminal, a drain terminal coupled to the serial data link output driver output terminal, and a source terminal coupled to a first voltage source having an output voltage corresponding to at least a voltage of a logic one output of the serial data link output driver, the at least one output drive circuit further including at least a first N channel output transistor having a gate terminal, a drain terminal coupled to the serial data link output driver output terminal in common with the drain terminal of the first P channel transistor, and a source terminal coupled to a second voltage source, the gate terminal of at least one of the first P channel output transistor and the first N channel output transistor being coupled to a second terminal of a corresponding capacitor of the at least one pair of capacitors of the capacitor pump circuit;
• a second output drive circuit including at least a second P channel output transistor having a gate terminal and a drain terminal, the drain terminal of the second P channel output transistor being coupled to the serial data link output driver output terminal, the gate terminal of the second P channel output transistor being coupled to a second terminal of a corresponding capacitor of the at least one pair of capacitors of the capacitor pump circuit;
• and
• at least one reset circuit having an input terminal coupled to the input logic circuit and having an output terminal coupled to the second terminal of the capacitor corresponding to the second P channel output transistor, the at least one reset circuit being configured to charge the corresponding capacitor to a voltage and polarity sufficient to hold the second P channel output transistor in an off state in correspondence with a logic level of the serial data input,
• wherein a change in the logic level of the serial data input switches the at least one reset circuit to an off state and changes the reference voltage of the first terminal of the at least one capacitor of the at least one pair of capacitors of the capacitor pump circuit from one logic level to another, thereby changing a magnitude of a voltage applied to the gate terminal of the second P channel transistor to exceed a gate threshold turn on voltage thereof, to turn on the second P channel output transistor and output a logic signal to the serial data link output driver output terminal, and
• wherein the input logic circuit is configured to alternately drive the first and second output drive circuits in correspondence with two oppositely phased clock signals having overlapping high logic levels for a predetermined time period.

A method of driving an output stage of a serial data link output driver having a pair of first P and N channel output transistors and a second P channel output transistor, each transistor of the pair of first P and N channel output transistors having drain terminals commonly coupled to an output terminal of the serial data link output driver, the second P channel output transistor having a drain terminal coupled to an output terminal of the serial data link output driver, the method comprising:

• providing a capacitor pump circuit including at least one pair of capacitors, each capacitor of the at least one pair of capacitors having a first terminal coupled to a corresponding output terminal of an input logic circuit, the capacitor pump circuit being configured for establishing a logic level voltage on the first terminal of at least one capacitor of the at least one pair of capacitors, the established logic level voltage corresponding to an opposing logic level to that of an input data bit, a second terminal of the at least one capacitor being coupled to a gate terminal of the second P channel output transistor, the capacitor pump circuit being further configured for establishing a voltage and polarity on the second terminal of the at least one capacitor relative to the first terminal sufficient to hold the second P channel output transistor in an off state;
• and
• driving, by the input logic circuit, the pair of first P and N channel output transistors alternatingly with the second P channel output transistor in correspondence with two oppositely phased clock signals having overlapping high logic levels for a predetermined time period,
• wherein, responsive to another input data bit having an opposing logic level, the logic level on the first terminal of the at least one capacitor of the at least one pair of capacitors of the capacitor pump circuit changes and thereby changes a magnitude of a voltage of the second terminal of the at least one capacitor relative to the first terminal thereof to a second voltage, the second voltage exceeding a gate threshold turn on voltage of the second P channel output transistor.

A serial data link output driver having serial data input and serial data output terminals, and further having first and second output drive circuits each having a pair of P and N channel output transistors, each of the P and N channel output transistors of the first output drive circuit having drain terminals commonly coupled to an output terminal of the serial data link output driver, each of the P and N channel output transistors of the second output drive circuit having drain terminals commonly coupled to the output terminal of the serial data link output driver, the serial data link output driver comprising:

• an input logic circuit having at least one input terminal coupled to the input terminal of the serial data link output driver for receiving serial data signal therefrom;
• at least one reset circuit having an input terminal coupled to an output terminal of the input logic circuit and an output terminal coupled to a gate terminal of at least one transistor of the pair of P and N channel output transistors of at least one output drive circuit of the first and second output drive circuits, the at least one reset circuit being configured to output a voltage and polarity thereof sufficient to hold the at least one transistor in an off state in correspondence with a logic level of the serial data input, the at least one reset circuit being inhibited from output of a voltage in correspondence with an opposing logic level of the serial data input;
• and
• a capacitor pump circuit having an input terminal thereof coupled to another output terminal of the input logic circuit and an output terminal thereof coupled to the gate terminal of the at least one transistor of the pair of P and N channel output transistors of the at least one output drive circuit, the capacitor pump circuit being configured to capacitively store the voltage outputted by the at least one reset circuit relative to a logic level voltage of the other output terminal of the input logic circuit, the capacitor pump circuit including at least one pair of capacitors, each capacitor of the at least one pair of capacitors having a first terminal coupled to an output terminal of the input logic circuit, at least one capacitor of the at least one pair of capacitors having a second terminal coupled to the gate terminal of the P channel output transistor of the second output drive circuit,
• wherein, in correspondence with the inhibited output of the at least one reset circuit, the logic level voltage of the other output terminal of the input logic circuit changes to an opposing logic level to thereby change a reference of the stored voltage and thereby establish a gate voltage of the at least one of the P and N channel output transistors of the one pair of P and N channel output transistors that exceeds a gate threshold turn on voltage thereof, and
• wherein the input logic circuit is configured to alternately drive the first and second output drive circuits in correspondence with two oppositely phased clock signals having overlapping high logic levels for a predetermined time period.