Self-calibration of delay circuits in asynchronous loops
AssigneeQUALCOMM Incorporated
InventorsShashank Rajendra Prasad, Patrick Isakanian
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Abstract
A calibration circuit has a delay loop, a counter and a latch. The delay loop that includes a delay circuit. The counter is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state. The latch is configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state. A number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter. In one example, the number of enabled unit delay elements is based on a difference between the multibit output of the counter and a multibit value expected to be generated when the delay circuit is operating nominally.
Claims20
A calibration circuit comprising:
- a delay loop that includes a delay circuit;
- a counter that is clocked by edges in a clock signal generated by the delay loop when an enable signal is in a first signaling state;
- and
- a latch configured to capture a multibit output of the counter when the enable signal transitions to a second signaling state,
- wherein a number of unit delay elements in the delay circuit are enabled based on the multibit output of the counter.
An apparatus comprising:
- means for counting cycles of a clock signal generated by a delay loop that includes a delay circuit, including series-connected flipflops clocked by edges in the clock signal, each flipflop of the series-connected flipflops providing one bit of a multibit output;
- and
- means for capturing the multibit output,
- wherein a number of unit delay elements in the delay circuit are enabled based on the multibit output.
A calibration method comprising:
- clocking a counter using edges in a clock signal generated by a delay loop that includes a delay circuit when an enable signal is in a first signaling state;
- capturing a multibit output of the counter when the enable signal transitions to a second signaling state;
- and
- enabling a number of unit delay elements in the delay circuit based on the multibit output of the counter.
Dependencies are inferred from the claim text.