Error remapping
AssigneeRambus Inc.
InventorChristopher Haywood
Life of this patent
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Abstract
Many error correction schemes fail to correct for double-bit errors and a module must be replaced when these double-bit errors occur repeatedly at the same address. This helps prevent data corruption. In an embodiment, the addresses for one of the memory devices exhibiting a single-bit error (but not the other also exhibiting a single bit error) is transformed before the internal memory arrays are accessed. This has the effect of moving one of the error prone memory cells to a different external (to the module) address such that there is only one error prone bit that is accessed by the previously double-bit error prone address. Thus, a double-bit error at the original address is remapped into two correctable single-bit errors that are at different addresses.
Claims14
A controller, comprising:
- a command/address interface to access a plurality of memory devices in parallel using transmitted single addresses transmitted by the command/address interface, the plurality of memory devices comprising a first set of memory devices and a second set of memory devices;
- and,
- address remapping configuration circuitry to store a value in at least one register internal to at least one of a registering clock driver and at least one of the plurality of memory devices to remap single addresses with respect to the first set of memory devices such that, in response to the transmitted single addresses, the first set of memory devices access first internal memory locations that are different from second internal memory locations accessed by the second set of memory devices.
A controller, comprising:
- a command/address interface to access a plurality of memory devices, disposed on a module, in parallel using transmitted single addresses transmitted by the command/address interface, the plurality of memory devices comprising a first set of memory devices and a second set of memory devices;
- error detection circuitry to detect errors are occurring in the first set of memory devices;
- and,
- address remapping configuration circuitry to, based on a detection of errors occurring in the first set of memory devices, store a value in at least one register internal to at least one of the plurality of memory devices to remap single addresses with respect to the first set of memory devices such that, in response to the transmitted single addresses, the first set of memory devices access first internal memory locations that are different from second internal memory locations accessed by the second set of memory devices.
Dependencies are inferred from the claim text.