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US 12,431,181 B2Granted
Memory device and memory system with table to determine refresh timing
AssigneeSK hynix Inc.
InventorMinseong Kim
Life of this patent
Estimating the term…
Abstract
A memory device includes a memory cell array including a plurality of rows; a time table including a plurality of fields respectively corresponding to the rows; and a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data.
Claims21
A memory device comprising:
- a memory cell array including a plurality of rows;
- a time table including a plurality of fields respectively corresponding to the rows;
- and
- a refresh control circuit configured to read field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, determine whether to issue a refresh request signal for the k-th row based on current clock data and the field data, and update the field data of the k-th field using the current clock data so that each of the plurality of fields stores a last access time of a corresponding row,
- wherein the refresh control circuit is configured to issue the refresh request signal whenever a difference between a decimal value of the updated field data for the last access time and a decimal value of the current clock data is greater than or equal to a preset refresh period, to thereby perform a refresh operation non-periodically according to an actual access point of each of the rows.
2 more elements
A memory device comprising:
- a memory cell array including a plurality of rows;
- a time table including a plurality of fields respectively corresponding to the rows, each field storing a last access time of a corresponding row as first field data;
- and
- a refresh control circuit configured to read the first field data from a k-th field of the time table according to an access command for a k-th row among the rows, where k is a natural number, and determine whether to issue a first refresh request signal for the k-th row based on current clock data and the first field data read from the k-th field,
- wherein the refresh control circuit is configured to issue the first refresh request signal whenever a difference between a decimal value of the updated field data for the last access time and a decimal value of the current clock data is greater than or equal to a preset refresh period, to thereby perform a refresh operation non-periodically according to an actual access point of each of the rows.
2 more elements
A memory system comprising:
- a memory controller;
- and
- a memory device including a plurality of memory cells, a plurality of word lines, and a table storing a latest access time for each word line,
- wherein the memory device is configured to:
- determine, through the table, a latest access time for a word line selected from among the plurality of the word lines;
- determine an interval between the latest access time and a current time;
- determine whether the interval is greater than or equal to a set refresh period;
- when it is determined that the interval is greater than or equal to the set refresh period, provide, to a memory controller, a refresh request signal;
- receive, from the memory controller, a refresh command in response to the refresh request signal;
- and
- refresh, in response to the refresh command, at least one word line corresponding to at least one refresh address including an address associated with the selected word line, by recharging capacitors of the memory cells coupled to the at least one word line, to thereby refresh each of the word lines non-periodically according to an actual access point of each word line.
8 more elements
Dependencies are inferred from the claim text.