Display device improving response speed of a gate clock signal or eliminating delay in the gate clock signal

A display device, comprising:

• a display panel including a plurality of pixels which are connected to a plurality of gate lines and a plurality of data lines and display a plurality of consecutive frames of images;
• a data driver which drives the data lines;
• a gate driver which drives the gate lines;
• a clock generator which outputs a gate clock signal which drives the gate driver and swings between a gate-on voltage and a gate-off voltage;
• and
• a signal controller which outputs a gate pulse signal which drives the clock generator and a data control signal which controls the data driver,
• wherein the clock generator comprises:
• a charge sharer which provides a voltage which swings between the gate-on voltage and the gate-off voltage, the charge sharer comprising first and second transistors connected in series with each other;
• a first switching circuit which provides one of the gate-on voltage and the gate-off voltage in response to the gate pulse signal,
• an impedance control circuit which is configured to delay the gate clock signal in a first period and advance the gate clock signal in a second period, and
• a second switching circuit which connects the impedance control circuit to one of the first transistor of the charge sharer and the first switching circuit,
• wherein the gate clock signal includes a first gate clock signal and a second gate clock signal, and the impedance control circuit re-matches the first and second gate clock signals by one of delaying or advancing one of the first and second gate clock signals during a period, which is after a manufacturing process of the display device, between consecutive frames of the plurality of consecutive frames that form the images displayed on the display device.