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AssigneeHitachi Astemo, Ltd.
InventorsYasuhiro Ikeda, Tadanobu Toba, Kenichi Shimbo, Atsushi Arata, Takeo Yamashita, Atsushi Ichige, Shinichi Nonaka
Estimating the term…
An arithmetic operation device executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit includes a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, and the arithmetic operation device includes a configuration control unit which causes the programmable logic unit to form, by partial reconfiguration, a test partition unit which separates the test target circuit and the non-test circuit, and a partition control unit which controls the test partition unit to test the test target circuit.
An arithmetic operation device which executes a test using a partially reconfigurable programmable logic unit, the programmable logic unit including a test target circuit which is a user circuit, and a non-test circuit which is a user circuit which is not the test target circuit, the arithmetic operation device comprising:
A testing method executed by a computer using a partially reconfigurable programmable logic unit, the testing method comprising:
Dependencies are inferred from the claim text.