Location-based global cache tiering
AssigneeDell Products L.P.
InventorsEarl Medeiros, Ramesh Doddaiah
Life of this patent
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AssigneeDell Products L.P.
InventorsEarl Medeiros, Ramesh Doddaiah
Estimating the term…
A method for use in a storage processor, comprising: generating or updating a cache metadata table that identifies a plurality of cache slots, for each of the plurality of cache slots, the cache metadata table including a different respective location identifier that indicates a location for that cache slot; receiving an I/O request that is associated with a logical block address; allocating a given one of the plurality of cache slots to the logical block address based on the respective location identifier that corresponds to the given cache slot; and executing the I/O request by using the given cache slot, wherein using the given cache slot includes identifying a memory address that is associated with the cache slot and executing at least one direct memory access (DMA) command based on the memory address.
A method for use in a storage processor, comprising:
A computing device, comprising:
A non-transitory computer-readable medium storing one or more processor-executable instructions, which, when executed by at least one processor of a computing device, causes the computing device to perform the operations of:
Dependencies are inferred from the claim text.