Out-of-order programming of first wordline in a physical unit of a memory device

A memory device comprising:

• a memory array comprising memory cells associated with a plurality of wordlines;
• and
• control logic operatively coupled to the memory array, the control logic to perform operations comprising:
• causing memory cells of a physical unit of the memory array to be programmed starting at a second wordline, which is adjacent to a first wordline of the memory array, and proceeding sequentially through a plurality of sequentially-ordered wordlines of the physical unit, wherein the plurality of sequentially-ordered wordlines comprises the first wordline and the second wordline and is a subset of the plurality of wordlines, and wherein the first wordline is associated with memory cells that are adjacent to one or more select gate (SG) transistors of the memory array, and the sequentially-ordered wordlines are numbered according to a distance away from the one or more SG transistors;
• and
• causing the memory cells associated with the first wordline to be programmed with metadata at a regular interval of a particular number of the plurality of sequentially-ordered wordlines having been programmed, wherein the memory cells associated with the first wordline are programmed at two or more of the regular intervals, and wherein the metadata is associated with programmed wordlines of the plurality of sequentially-ordered wordlines.