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US 12,430,201 B2Granted
Multi-processor bridge with cache allocate awareness
AssigneeTexas Instruments Incorporated
InventorsKai Chirca, Daniel Wu, Matthew David Pierson
Life of this patent
Estimating the term…
Abstract
Techniques for loading data, comprising receiving a memory management command to perform a memory management operation to load data into the cache memory before execution of an instruction that requests the data, formatting the memory management command into one or more instruction for a cache controller associated with the cache memory, and outputting an instruction to the cache controller to load the data into the cache memory based on the memory management command.
Claims19
A system comprising:
- a processor package including a plurality of processors and a cache memory coupled to the plurality of processors;
- and
- a shared memory controller coupled to the processor package and configured to:
- receive a memory management command including a first indication of a memory operation and a second indication of a memory location in the cache memory, wherein the first indication specifies that the memory operation is a prewarming operation for the memory location in the cache memory;
- format the memory management command into a formatted command;
- route the formatted command to the processor package;
- and
- receive a response from the processor package indicating that the memory operation was successful.
5 more elements
A method comprising:
- receiving a first memory management command including a first indication of a memory operation and a second indication of a memory location in a cache memory in a processor package, wherein the first indication specifies that the memory operation is a prewarming operation for the memory location in the cache memory;
- formatting the first memory management command into a formatted command;
- routing the formatted command to the processor package;
- and
- receiving a response from the processor package indicating that the memory operation was successful.
2 more elements
A system comprising:
- a processor package including:
- a plurality of processors;
- a cache memory coupled to the plurality of processors;
- and
- a cache memory controller coupled to the cache memory, wherein the processor package is configured to:
- schedule a second process for execution after a currently running first process;
- and
- issue a first prewarming command to prewarm a location in the cache memory before switching from the currently running first process to the second process;
- and
- a shared memory controller coupled to the processor package and configured to:
- format the first prewarming command into a first formatted command;
- route the first formatted command to the cache memory controller;
- and
- receive a response from the cache memory controller indicating that a loading of data into the location was successful.
11 more elements
Dependencies are inferred from the claim text.