Technologies for interconnect address remapper with event recognition and register management

An integrated circuit for executing instructions comprising:

• a processor core configured to execute instructions, wherein the processor core includes:
• one or more pair of region registers configured to define a From Address range and a To Address;
• a region register configured to store a number of regions defined in the integrated circuit, wherein a region in defined by a pair of region registers;
• interrupt enable registers dynamically interacting with each of the one or more pair of region registers;
• and
• event flags associated with each of the one or more pair of region registers, configured to indicate a matching condition for address ranges;
• an interconnection system configured to handle transactions from the processor core related to the execution of the instructions;
• an interconnect address remapper configured to translate an address associated with a transaction using the one or more pair of region registers;
• and
• an interrupt controller configured to receive an interrupt signal from the interconnect address remapper when the interrupt enable registers are enabled and at least one of the event flags is raised when at least one of the one or more pair of region registers matches the address associated with the transaction.