Macro and SRAM bit cell cooptimizatoin for performance (long/shortwordline combo SRAM)

A memory device comprising:

• a memory array comprising a plurality of memory cells including a first memory cell and a second memory cell, each memory cell of the plurality of memory cells connected to:
• a word line extending in a first direction;
• and
• a bit line extending in a second direction that is perpendicular to the first direction and having a first bit line portion and a second bit line portion, the first bit line portion having a first width in the first direction and the second bit line portion having a second width in the first direction;
• wherein the first width is substantially same as the second width, and
• wherein the first bit line portion of the first memory cell abuts the second bit line portion of the second memory cell.

A memory device comprising:

• a memory array comprising a plurality of memory cells including a first memory cell and a second memory cell, each memory cell of the plurality of memory cells connected to:
• a word line extending in a first direction;
• and
• a bit line extending in a second direction that is perpendicular to the first direction and having a first bit line portion and a second bit line portion;
• wherein the first bit line portion and the second bit line portion of the first memory cell are spaced apart from one another in the first direction, and the first bit line portion of the first memory cell abuts the second bit line portion of the second memory cell.