Twisted differential compensation for routing high-speed signals near power delivery inductors and system miniaturization

A method for routing differential signals in a printed circuit board (PCB) comprising a multi-layer substrate and including a top plane to which an inductor is operatively coupled, the inductor having a central axis disposed perpendicular to the top plane and having a centerline projected onto the top plane, the method comprising:

• routing a P signal of the differential signals along a first signal path comprising a P trace;
• and
• routing a N signal of the differential signals along a second signal path comprising an N trace,
• wherein each of the P trace and N trace are routed through one or more layers in the multi-layer substrate and employ a twisted portion proximate to the centerline of the inductor under which portions of the P and N traces are swapped and the traces are configured such that a level of noise induced by the inductor and coupled into the P trace and the N trace is approximately equal.

A compute device comprising:

• a processor, including a high-speed input-output (IO) interface, mounted to a printed circuit board (PCB) comprising a multi-layer substrate having a plurality of layers and having a plurality of traces and vias formed therein including power and ground traces used to provide power to components in the compute device including the processor;
• a power supply circuit comprising a plurality of components mounted to the PCB including an inductor having a central axis disposed perpendicular to a top plane of the PCB and having a centerline projected onto the top plane, the power supply circuit having outputs coupled to the power and ground traces,
• wherein the plurality of traces in the PCB include a differential pair of traces comprising a P trace and an N trace being routed through one or more layers in the multi-layer substrate and employ a twisted portion proximate to the centerline of the inductor under which portions of the P and N traces are swapped horizontally in a layer parallel to the top plane or are swapped vertically by swapping layers, and
• wherein the P trace and the N trace are coupled between the high-speed IO interface on the processor and one of an interface of an I/O component or a high-speed IO connector mounted or operatively coupled to the PCB.