Reconfigurable processor-based programmable switching fabric and programmable data plane chip

A programmable data plane chip, comprising a reconfigurable processor-based programmable switching fabric, wherein the reconfigurable processor-based programmable switching fabric comprises:

• a first side pathway configured to transmit a Packet Header Vector (PHV);
• a second side pathway configured to transmit data other than the PHV and a control signal;
• and
• a reconfigurable processor sequence comprising a plurality of reconfigurable processors, the plurality of reconfigurable processors being in communication with each other via the first side pathway and the second side pathway, wherein:
• each of the plurality of reconfigurable processors is reconfigurable as a pipeline stage or a Run-To-Complete (RTC) processor;
• a data pathway for transmitting the PHV is provided between each pair of adjacent reconfigurable processors;
• the data pathway is opened, when the reconfigurable processors at two ends of the data pathway are reconfigured as pipeline stages, to connect the two pipeline stages to a complete pipeline;
• and
• the data pathway is closed when the reconfigurable processors at two ends of the data pathway are not both reconfigured as the pipeline stages, and one of the reconfigurable processors reconfigured as the RTC processor is connected via the first side pathway.